HT82K70E-L datasheet(36/59 Pages) HOLTEK

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HT82K70E-L/HT82K70A-L/HT82K76E-L

Rev. 1.20

February 1, 2011

In the Master Mode, the Master will always generate the

clock signal. The clock and data transmission will be ini-

tiated after data has been written to the SBDR register.

In the Slave Mode, the clock signal will be received from

an external master device for both data transmission or

reception. The following sequences show the order to

be followed for data transfer in both Master and Slave

Mode:

· Master Mode

Step 1. Select the clock source using the CKS bit in

the SBCR control register

Step 2. Setup the M0 and M1 bits in the SBCR control

required Baud rate. Values of 00, 01 or 10 can

be selected.

Step 3. Setup the CSEN bit and setup the MLS bit to

choose if the data is MSB or LSB first,

this must be same as the Slave device.

Step 4. Setup the SBEN bit in the SBCR control

Step 5. For write operations: write the data to the

SBDR register, which will actually place the

data into the TXRX buffer. Then use the SCK

and SCS lines to output the data.

Goto to step 6.For read operations: the data

transferred in on the SDI line will be stored

in the TXRX buffer until all the data has been

received at which point it will be latched into

the SBDR register.

Step 6. Check the WCOL bit, if set high then a

collision error has occurred so return to step5.

If equal to zero then go to the following step.

Step 7. Check the TRF bit or wait for an SPI serial bus

interrupt.

Step 8. Read data from the SBDR register

Step 9. Clear TRF

Step10. step 5

· Slave Mode

Step 1. The CKS bit has a don

¢t care value in the

slave mode.

Step 2. Setup the M0 and M1 bits to 11 to select the

Slave Mode. The CKS bit is don

¢t care.

Step 3. Setup the CSEN bit and setup the MLS bit to

choose if the data is MSB or LSB first,

this must be same as the Master device.

Step 4. Setup the SBEN bit in the SBCR control

Step 5. For write operations: write data to the SBCR

the TXRX register, then wait for the master

clock and SCS signal. After this goto step 6.

For read operations: the data transferred in

on the SDI line will be stored in the TXRX

buffer until all the data has been received

at which point it will be latched into the SBDR

Step 6. Check the WCOL bit, if set high then a

collision error has occurred so return to step5.

If equal to zero then go to the following step.

Step 7. Check the TRF bit or wait for an SPI serial bus

interrupt.

Step 8. Read data from the SBDR register

Step 9. Clear TRF

Step10. step 5

SPI Configuration Options and Status Control

Several configuration options exist for the SPI Interface

function which must be setup during device programming.

One option is to enable the operation of the WCOL, write

collision bit, in the SBCR register. Another option exists to

select the clock polarity of the SCK line. A configuration

option also exists to disable or enable the operation of the

CSEN bit in the SBCR register. If the configuration option

disables the CSEN bit then this bit cannot be used to affect

overall control of the SPI Interface.

SPI include four pins , can share I/O mode status . The

status control combine with four bits for WSR and SBCR

and CSEN, SBEN for SBCR register.

Control Bit for Register

SPI Share Function Pins Status

SPI_EN

SPI_CSEN

SBEN

CSEN

SCS

SCK

SDO

SDI

I/O mode

SPI mode (Z)

I/O mode

SPI mode

SPI mode (Z)

SPI mode

SPI mode (Z)

SPI mode

SPI mode (Z)

Note:

X: don

¢t care

(Z) floating

HT82K70E-L Datasheet(PDF) 36 Page - Holtek Semiconductor Inc

HT82K70E-L Datasheet(HTML) 36 Page - Holtek Semiconductor Inc

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