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R5F562TABDFM Datasheet(PDF) 68 Page - Renesas Technology Corp |
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R5F562TABDFM Datasheet(HTML) 68 Page - Renesas Technology Corp |
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68 / 94 page ![]() R01DS0096EJ0100 Rev.1.00 Page 68 of 92 Apr 20, 2011 RX62T Group 5. Electrical Characteristics 5.3.2 Control Signal Timing Note 1. Do not allow a reset by the signal on the RES# pin during programming or erasure of the ROM or data-flash memory or during blank checking of the data-flash memory. For details, see section 30.12, Usage Notes in section 30, ROM (Flash Memory for Code Storage). Note 2. Both the time and the number of cycles should satisfy the specifications. Note 3. This is to specify the FCU reset and the WDT reset. Note 4. ICLK cycles. Figure 5.5 Reset Input Timing Figure 5.6 NMI Interrupt Input Timing Figure 5.7 IRQ Interrupt Input Timing Table 5.7 Control Signal Timing Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min. Max. Unit Test Conditions RES# pulse width (except for programming or erasure of the ROM or data-flash memory or blank checking of the data-flash memory*1) tRESW*2 20 - tIcyc*4 Figure 5.5 1.5 - s Internal reset time*3 tRESW2 35 - s NMI pulse width tNMIW 200 - ns Figure 5.6 IRQ pulse width tIRQW 200 - ns Figure 5.7 RES# tRESW NMI tNMIW IRQ tIRQW |
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