CY8C53_11 datasheet(40/106 Pages) CYPRESS

40 / 106 page

PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 40 of 106

Figure 7-13. Digital System Interconnect

Interrupt and DMA routing is very flexible in the CY8C53

programmable architecture. In addition to the numerous fixed

function peripherals that can generate interrupt requests, any

data signal in the UDB array routing can also be used to generate

request.

single

peripheral

may

generate

multiple

independent interrupt requests simplifying system and firmware

design. Figure 7-14 shows the structure of the IDMUX

(Interrupt/DMA Multiplexer).

Figure 7-14. Interrupt and DMA Processing in the IDMUX

7.4.1 I/O Port Routing

There are a total of 20 DSI routes to a typical 8-bit I/O port, 16

for data and four for drive strength control.

When an I/O pin is connected to the routing, there are two

primary connections available, an input and an output. In

conjunction with drive strength control, this can implement a

bidirectional I/O pin. A data output signal has the option to be

single synchronized (pipelined) and a data input signal has the

option to be double synchronized. The synchronization clock is

the system clock (see Figure 6-1). Normally all inputs from pins

are synchronized as this is required if the CPU interacts with the

signal or any signal derived from it. Asynchronous inputs have

rare uses. An example of this is a feed through of combinational

PLD logic from input pins to output pins.

Figure 7-15. I/O Pin Synchronization Routing

Figure 7-16. I/O Pin Output Connectivity

There are four more DSI connections to a given I/O port to

implement dynamic output enable control of pins. This

connectivity gives a range of options, from fully ganged 8-bits

controlled by one signal, to up to four individually controlled pins.

The output enable signal is useful for creating tri-state

bidirectional pins and buses.

UDB ARRAY

Digital System Routing I/F

CAN

Interrupt

Controller

I2C

IO Port

Pins

DMA

Controller

IO Port

Pins

Del-Sig

Comparators

DACs

SC/CT

Blocks

Global

Clocks

Global

Clocks

Timer

Counters

DMA termout (IRQs)

DMA

Controller

Interrupt

Controller

Fixed Function IRQs

Edge

Detect

Edge

Detect

IRQs

UDB Array

Fixed Function DRQs

DRQs

Interrupt and DMA Processing in IDMUX

Port i

PIN 0

PIN1

PIN2

PIN3

PIN4

PIN5

PIN6

PIN7

8 IO Data Output Connections from the

UDB Array Digital System Interface

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