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PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 44 of 106

7.8 I2C

The I2C peripheral provides a synchronous two wire interface

designed to interface the PSoC device with a two wire I2C serial

communication bus. The bus is compliant with Philips ‘The I2C

Specification’ version 2.1. Additional I2C interfaces can be

instantiated using Universal Digital Blocks (UDBs) in PSoC

Creator, as required.

To eliminate the need for excessive CPU intervention and

overhead, I2C specific support is provided for status detection

and generation of framing bits. I2C operates as a slave, a master,

or multimaster (Slave and Master). In slave mode, the unit

always listens for a start condition to begin sending or receiving

data. Master mode supplies the ability to generate the Start and

Stop conditions and initiate transactions. Multimaster mode

provides clock synchronization and arbitration to allow multiple

masters on the same bus. If Master mode is enabled and Slave

mode is not enabled, the block does not generate interrupts on

externally generated Start conditions. I2C interfaces through the

DSI routing and allows direct connections to any GPIO or SIO

pins.

I2C features include:

Slave and Master, Transmitter, and Receiver operation

Byte processing for low CPU overhead

Interrupt or polling CPU interface

Support for bus speeds up to 1 Mbps (3.4 Mbps in UDBs)

7 or 10-bit addressing (10-bit addressing requires firmware

support)

SMBus operation (through firmware support - SMBus

supported in hardware in UDBs)

Data transfers follow the format shown in Figure 7-22. After the

START condition (S), a slave address is sent. This address is 7

bits long followed by an eighth bit which is a data direction bit

(R/W) - a 'zero' indicates a transmission (WRITE), a 'one'

indicates a request for data (READ). A data transfer is always

terminated by a STOP condition (P) generated by the master.

However, if a master still wishes to communicate on the bus, it

can generate a repeated START condition (Sr) and address

another slave without first generating a STOP condition. Various

combinations of read/write formats are then possible within such

a transfer.

Figure 7-22. I2C Complete Transfer Timing

SDA

SCL

1 - 7

START

Condition

ADDRESS

R/W

ACK

DATA

ACK

DATA

ACK

STOP

Condition

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