CY8C53_11 datasheet(93/106 Pages) CYPRESS

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PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 93 of 106

11.8.3 SWD Interface

11.8.4 TPIU Interface

Table 11-63. SWD Interface AC Specifications[34]

Parameter

Description

Conditions

Min

Typ

Max

Units

f_SWDCK

SWDCLK frequency

3.3 V

≤ V

DDD ≤ 5 V

–

12[35]

MHz

2.7 V

≤ V

DDD < 3.3 V

–

7[35]

MHz

2.7 V

≤ V

DDD < 3.3 V, SWD over

USBIO pins

––

5.5[35]

MHz

T_SWDI_setup SWDIO input setup before SWDCK high T = 1/f_SWDCK max

T/4

–

T_SWDI_hold

SWDIO input hold after SWDCK high

T = 1/f_SWDCK max

T/4

–

T_SWDO_valid SWDCK high to SWDIO output

T = 1/f_SWDCK max

–

2T/5

T_SWDO_hold SWDIO output hold after SWDCK low

T = 1/f_SWDCK max

T/4

–

Notes

34. Based on device characterization (Not production tested).

35. f_SWDCK must also be no more than 1/3 CPU clock frequency.

36. SWV signal frequency and bit rate are limited by GPIO output frequency, see “GPIO AC Specifications” on page 64.

Table 11-64. TPIU Interface AC Specifications[36]

Parameter

Description

Conditions

Min

Typ

Max

Units

SWV bit rate

–

Mbit

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