CY8C53_11 datasheet(31/106 Pages) CYPRESS

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PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 31 of 106

6.4.11 Adjustable Output Level

This section applies only to SIO pins. SIO port pins support the

ability to provide a regulated high output level for interface to

external signals that are lower in voltage than the SIO’s

respective VDDIO. SIO pins are individually configurable to output

either the standard VDDIO level or the regulated output, which is

based on an internally generated reference. Typically a voltage

DAC (VDAC) is used to generate the reference (see Figure

6-12). The “DAC” section on page 52 has more details on VDAC

use and reference routing to the SIO pins. Resistive pull-up and

pull-down drive modes are not available with SIO in regulated

output mode.

6.4.12 Adjustable Input Level

This section applies only to SIO pins. SIO pins by default support

the standard CMOS and LVTTL input levels but also support a

differential mode with programmable levels. SIO pins are

grouped into pairs. Each pair shares a reference generator block

which, is used to set the digital input buffer reference level for

interface to external signals that differ in voltage from VDDIO. The

reference sets the pins voltage threshold for a high logic level

(see Figure 6-12). Available input thresholds are:

0.5 × VDDIO

0.4 × VDDIO

0.5 × VREF

VREF

Typically a voltage DAC (VDAC) generates the VREF reference.

“DAC” section on page 52 has more details on VDAC use and

reference routing to the SIO pins.

Figure 6-12. SIO Reference for Input and Output

6.4.13 SIO as Comparator

This section applies only to SIO pins. The adjustable input level

feature of the SIOs as explained in the Adjustable Input Level

section can be used to construct a comparator. The threshold for

the comparator is provided by the SIO's reference generator. The

reference generator has the option to set the analog signal

routed through the analog global line as threshold for the

comparator. Note that a pair of SIO pins share the same

threshold.

The digital input path in Figure 6-9 on page 28 illustrates this

functionality. In the figure, ‘Reference level’ is the analog signal

routed through the analog global. The hysteresis feature can

also be enabled for the input buffer of the SIO, which increases

noise immunity for the comparator.

6.4.14 Hot Swap

This section applies only to SIO pins. SIO pins support ‘hot swap’

capability to plug into an application without loading the signals

that are connected to the SIO pins even when no power is

applied to the PSoC device. This allows the unpowered PSoC to

maintain a high impedance load to the external device while also

preventing the PSoC from being powered through a GPIO pin’s

protection diode.

6.4.15 Over Voltage Tolerance

All I/O pins provide an over voltage (VDDIO < VIN < VDDA)

tolerance feature at any operating VDD.

There are no current limitations for the SIO pins as they present

a high impedance load to the external circuit.

The GPIO pins must be limited to 100 µA using a current limiting

resistor. GPIO pins clamp the pin voltage to approximately one

diode above the VDDIO supply.

In case of a GPIO pin configured for analog input/output, the

analog voltage on the pin must not exceed the VDDIO supply

voltage to which the GPIO belongs.

A common application for this feature is connection to a bus such

as I2C where different devices are running from different supply

voltages. In the I2C case, the PSoC chip is configured into the

Open Drain, Drives Low mode for the SIO pin. This allows an

external pull-up to pull the I2C bus voltage above the PSoC pin

supply. For example, the PSoC chip could operate at 2.7 V, and

an external device could run from 5 V. Note that the SIO pin’s VIH

and VIL levels are determined by the associated VDDIO supply

pin.

The I/O pin must be configured into a high impedance drive

mode, open drain low drive mode, or pull-down drive mode, for

over voltage tolerance to work properly. Absolute maximum

ratings for the device must be observed for all I/O pins.

6.4.16 Reset Configuration

At reset, all I/Os are reset to the High Impedance Analog state.

6.4.17 Low Power Functionality

In all low power modes the I/O pins retain their state until the part

is awakened and changed or reset. To awaken the part, use a

pin interrupt, because the port interrupt logic continues to

function in all low power modes.

Drive

Logic

Driver

Vhigh

Reference

Generator

SIO_Ref

Digital

Input

Digital

Output

Input Path

Output Path

Vinref

Voutref

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