CY8C53_11 datasheet(10/106 Pages) CYPRESS

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PRELIMINARY

PSoC® 5: CY8C53 Family Datasheet

Document Number: 001-66237 Rev. *A

Page 10 of 106

4. CPU

4.1 ARM Cortex-M3 CPU

The CY8C53 family of devices has an ARM Cortex-M3 CPU core. The Cortex-M3 is a low power 32-bit three-stage pipelined Harvard

architecture CPU that delivers 1.25 DMIPS/MHz. It is intended for deeply embedded applications that require fast interrupt handling

features.

Figure 4-1. ARM Cortex-M3 Block Diagram

The Cortex-M3 CPU subsystem includes these features:

ARM Cortex-M3 CPU

Programmable NVIC, tightly integrated with the CPU core

Full-featured debug and trace module, tightly integrated with

the CPU core

Up to 128 KB of flash memory, 2 KB of EEPROM, and 32 KB

of SRAM

Cache controller

Peripheral HUB (PHUB)

DMA controller

4.1.1 Cortex-M3 Features

The Cortex-M3 CPU features include:

4-GB address space. Predefined address regions for code,

data, and peripherals. Multiple buses for efficient and

simultaneous accesses of instructions, data, and peripherals.

The Thumb®-2 instruction set, which offers ARM-level

performance at Thumb-level code density. This includes 16-bit

and 32-bit instructions. Advanced instructions include:

Bit-field control

Hardware multiply and divide

Saturation

If-Then

Wait for events and interrupts

Exclusive access and barrier

Special register access

The Cortex-M3 does not support ARM instructions.

Nested

Vectored

Interrupt

Controller

(NVIC)

Debug Block

(SWD)

Trace Port

Interface Unit

(TPIU)

Interrupt Inputs

SWD

SWV

Cortex M3 CPU Core

I- Bus

S-Bus

D- Bus

256 KB

Flash

Cache

32 KB

SRAM

DMA

AHB Bridge and Bus Matrix

PHUB

GPIO

Prog.

Digital

Prog.

Analog

Special

Functions

Peripherals

AHB Spokes

AHB

Bus

Matrix

Cortex M3 Wrapper

C- Bus

Bus

Matrix

32 KB

SRAM

Bus

Matrix

Data

Watchpoint and

Trace (DWT)

Instrumentation

Trace Module

(ITM)

Flash Patch and

Breakpoint

(FPB)

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