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WM8737CLGEFL/R Datasheet(PDF) 26 Page - Wolfson Microelectronics plc |
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WM8737CLGEFL/R Datasheet(HTML) 26 Page - Wolfson Microelectronics plc |
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26 / 40 page ![]() WM8737L Production Data w PD, Rev 4.4, January 2012 26 LEFT CHANNEL RIGHT CHANNEL ADCLRC BCLK ADCDAT 1/fs n 3 2 1 n-2 n-1 LSB MSB n 3 2 1 n-2 n-1 LSB MSB 1 BCLK 1 BCLK Figure 12 I 2S Justified Audio Interface (assuming n-bit word length) In DSP mode, the left channel MSB is available on either the 1 st or 2nd rising edge of BCLK (selectable by LRP) following a rising edge of ADCLRC. Right channel data immediately follows left channel data. Depending on word length, BCLK frequency and sample rate, there may be unused BCLK cycles between the LSB of the right channel data and the next sample. Figure 13 DSP Mode A Mater Mode Figure 14 DSP Mode B, Master Mode Audio Interface |
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