JS28F128P33TF70A datasheet(37/88 Pages) MICROCHIP

37 / 88 page

Datasheet

Jul 2011

Order Number:208034-04

P33-65nm SBC

Table 14: End of Wordline Data and WAIT state Comparison

11.1.4

WAIT Polarity (RCR.10)

The WAIT Polarity bit (WP), RCR.10 determines the asserted level (VOH or VOL) of WAIT.

When WP is set, WAIT is asserted high. When WP is cleared, WAIT is asserted low

(default). WAIT changes state on valid clock edges during active bus cycles (CE#

asserted, OE# asserted, RST# deasserted).

11.1.5

WAIT Signal Function

The WAIT signal indicates data valid when the device is operating in synchronous mode

(RCR.15=0). The WAIT signal is only “deasserted” when data is valid on the bus.

When the device is operating in synchronous non-array read mode, such as read

status, read ID, or read query. The WAIT signal is also “deasserted” when data is valid

on the bus.

WAIT behavior during synchronous non-array reads at the end of word line works

correctly only on the first data access.

When the device is operating in asynchronous page mode, asynchronous single word

read mode, and all write operations, WAIT is set to a deasserted state as determined

by RCR.10. See Figure 18, “Asynchronous Single-Word Read (ADV# Latch)” on

page 51, and Figure 19, “Asynchronous Page-Mode Read Timing” on page 52.

Latency Count

P33-130nm

P33-65nm

Data States

WAIT States

Data States

WAIT States

Not Supported

0 to 1

0 to 2

0 to 3

0 to 4

0 to 5

0 to 6

JS28F128P33TF70A Datasheet(PDF) 37 Page - Microchip Technology