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JS28F128P33TF70A Datasheet(PDF) 64 Page - Microchip Technology |
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JS28F128P33TF70A Datasheet(HTML) 64 Page - Microchip Technology |
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64 / 88 page ![]() P33-65nm Datasheet Jul 2011 64 Order Number: 208034-04 A.1.4 Device Geometry Definition Table 33: Device Geometry Definition Offset Length Description Add Hex Code Value 27h 1 “n” such that device size = 2n in number of bytes 27: See Table Below 28h 2 Flash device interface code assignment: "n" such that n+1 specifies the bit field that represents the flash device width capabilities as described in the table: 7 654 321 0 _ _ _ _ x64 x32 x16 x8 28: -01 x16 15 14 13 12 11 10 9 8 _ ___ ___ _ 29: -00 2Ah 2 “n” such that maximum number of bytes in write buffer = 2n 2A: -09 512 2B: -00 2Ch 1 Number of erase block regions (x) within device: 1. x = 0 means no erase blocking; the device erases in bulk 2. x specifies the number of device regions with one or more contiguous same-size erase blocks. 3. Symmetrically blocked partitions have one blocking region 2C: See Table Below 2D 4 Erase Block Region 1 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 2D: See Table Below 2E: 2F: 30: 31h 4 Erase Block Region 2 Information bits 0-15 = y, y+1 = number of identical-size erase blocks bits 16-31 = z, region erase block(s) size are z x 256 bytes 31: See Table Below 32: 33: 34: 35h 4 Reserved for future erase block region information 35: See Table Below 36: 37: 38: Address 64-Mbit 128-Mbit Address 64-Mbit 128-Mbit -B -T -B -T -B -T -B -T 27: -17 -17 -18 -18 30: -00 -02 -00 -02 28: -01 -01 -01 -01 31: -3E -03 -7E -03 29: -00 -00 -00 -00 32: -00 -00 -00 -00 2A -09 -09 -09 -09 33: -00 -80 -00 -80 2B -00 -00 -00 -00 34: -02 -00 -02 -00 2C: -02 -02 -02 -02 35: -00 -00 -00 -00 2D: -03 -3E -03 -7E 36: -00 -00 -00 -00 2E: -00 -00 -00 -00 37: -00 -00 -00 -00 2F: -80 -00 -80 -00 38: -00 -00 -00 -00 |
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