PIC16F87X datasheet(70/218 Pages) MICROCHIP

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PIC16F87X

DS30292D-page 70

 1998-2013 Microchip Technology Inc.

9.1.1

MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCK. The master determines

when the slave (Processor 2, Figure 9-5) is to broad-

cast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPBUF register is written to. If the SPI

module is only going to receive, the SDO output could

be disabled (programmed as an input). The SSPSR

SDI pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPBUF register as

if a normal received byte (interrupts and status bits

appropriately set). This could be useful in receiver

applications as a “line activity monitor”.

The clock polarity is selected by appropriately program-

ming bit CKP (SSPCON<4>). This then, would give

waveforms for SPI communication as shown in

Figure 9-6, Figure 9-8 and Figure 9-9, where the MSb is

transmitted first. In Master mode, the SPI clock rate (bit

rate) is user programmable to be one of the following:

•FOSC/4 (or TCY)

•FOSC/16 (or 4 • TCY)

•FOSC/64 (or 16 • TCY)

• Timer2 output/2

This allows a maximum bit clock frequency (at 20 MHz)

of 5.0 MHz.

Figure 9-6 shows the waveforms for Master mode.

When CKE = 1, the SDO data is valid before there is a

clock edge on SCK. The change of the input sample is

shown based on the state of the SMP bit. The time

when the SSPBUF is loaded with the received data is

shown.

FIGURE 9-2:

SPI MODE TIMING, MASTER MODE

SCK (CKP = 0,

SDI (SMP = 0)

SSPIF

bit7

bit6

bit5

bit4

bit3

bit2

bit1

bit0

SDI (SMP = 1)

SCK (CKP = 0,

SCK (CKP = 1,

SDO

bit7

bit0

CKE = 0)

CKE = 1)

CKE = 0)

CKE = 1)

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