30F4013 datasheet(30/228 Pages) MICROCHIP

30 / 228 page

dsPIC30F3014/4013

DS70138G-page 30

 2010 Microchip Technology Inc.

3.2

Data Address Space

The core has two data spaces. The data spaces can be

considered either separate (for some DSP instructions),

or as one unified linear address range (for MCU instruc-

tions). The data spaces are accessed using two Address

Generation Units (AGUs) and separate data paths.

3.2.1

DATA SPACE MEMORY MAP

The data space memory is split into two blocks, X and

Y data space. A key element of this architecture is that

Y space is a subset of X space, and is fully contained

within X space. In order to provide an apparent Linear

Addressing space, X and Y spaces have contiguous

addresses.

When executing any instruction other than one of

the MAC class of instructions, the X block consists of the

64-Kbyte data address space (including all Y addresses).

When executing one of the MAC class of instructions, the

X block consists of the 64-Kbyte data address space

excluding the Y address block (for data reads only). In

other words, all other instructions regard the entire data

memory as one composite address space. The MAC

class instructions extract the Y address space from data

space and address it using EAs sourced from W10 and

W11. The remaining X data space is addressed using W8

and W9. Both address spaces are concurrently accessed

only with the MAC class instructions.

The data space memory map is shown in Figure 3-7.

FIGURE 3-7:

dsPIC30F3014/dsPIC30F4013 DATA SPACE MEMORY MAP

0x0000

0x07FE

0x0BFE

0xFFFE

LSB

Address

16 bits

LSB

MSB

Address

0x0001

0x07FF

0x0BFF

0xFFFF

0x8001

0x8000

Optionally

Mapped

into Program

Memory

0x0FFF

0x0FFE

0x1000

0x1001

0x0801

0x0800

0x0C01

0x0C00

Near

Data

0x1FFE

0x1FFF

2 Kbyte

SFR Space

2 Kbyte

SRAM Space

8 Kbyte

Space

X Data

Unimplemented (X)

SFR Space

X Data RAM (X)

Y Data RAM (Y)

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