30F4013 datasheet(99/228 Pages) MICROCHIP

99 / 228 page

 2010 Microchip Technology Inc.

DS70138G-page 99

dsPIC30F3014/4013

15.0

SPI MODULE

The Serial Peripheral Interface (SPI) module is a syn-

chronous serial interface. It is useful for communicating

with other peripheral devices, such as EEPROMs, shift

registers, display drivers and A/D converters, or other

microcontrollers. It is compatible with Motorola’s SPI

and

SIOP

interfaces.

The

dsPIC30F3014

and

dsPIC30F4013 devices feature one SPI module, SPI1.

15.1

Operating Function Description

Each SPI module consists of a 16-bit shift register,

SPIxSR (where x = 1 or 2), used for shifting data in and

out, and a buffer register, SPIxBUF. A control register,

SPIxCON, configures the module. Additionally, a status

The serial interface consists of 4 pins: SDIx (Serial

Data Input), SDOx (Serial Data Output), SCKx (Shift

Clock Input or Output), and SSx (Active-Low Slave

Select).

In Master mode operation, SCKx is a clock output but

in Slave mode, it is a clock input.

A series of eight (8) or sixteen (16) clock pulses shift

out

bits

from

the

SPIxSR

SDOx

and

simultaneously shift in data from SDIx pin. An interrupt

is generated when the transfer is complete and the cor-

responding interrupt flag bit (SPI1IF or SPI2IF) is set.

This interrupt can be disabled through an interrupt

enable bit (SPI1IE or SPI2IE).

The receive operation is double-buffered. When a com-

plete byte is received, it is transferred from SPIxSR to

SPIxBUF.

If the receive buffer is full when new data is being trans-

ferred from SPIxSR to SPIxBUF, the module sets the

SPIROV bit, indicating an overflow condition. The

transfer of the data from SPIxSR to SPIxBUF is not

completed and new data is lost. The module does not

respond to SCL transitions while SPIROV is ‘1’,

effectively disabling the module until SPIxBUF is read

by user software.

Transmit writes are also double-buffered. The user

writes to SPIxBUF. When the master or slave transfer

is completed, the contents of the shift register (SPIxSR)

are moved to the receive buffer. If any transmit data has

been written to the buffer register, the contents of the

transmit buffer are moved to SPIxSR. The received

data is thus placed in SPIxBUF and the transmit data in

SPIxSR is ready for the next transfer.

In Master mode, the clock is generated by prescaling

the system clock. Data is transmitted as soon as a

value is written to SPIxBUF. The interrupt is generated

at the middle of the transfer of the last bit.

In Slave mode, data is transmitted and received as

external clock pulses appear on SCKx. Again, the inter-

rupt is generated when the last bit is latched. If SSx

control is enabled, then transmission and reception are

enabled only when SSx = low. The SDOx output is

disabled in SSx mode with SSx high.

The clock provided to the module is (FOSC/4). This

clock is then prescaled by the primary (PPRE<1:0>)

and the secondary (SPRE<2:0>) prescale factors. The

CKE bit determines whether transmit occurs on transi-

tion from active clock state to Idle clock state, or vice

versa. The CKP bit selects the Idle state (high or low)

for the clock.

15.1.1

WORD AND BYTE

COMMUNICATION

A control bit, MODE16 (SPIxCON<10>), allows the

module to communicate in either 16-bit or 8-bit mode.

16-bit operation is identical to 8-bit operation except

that the number of bits transmitted is 16 instead of 8.

The user software must disable the module prior to

changing the MODE16 bit. The SPI module is reset

when the MODE16 bit is changed by the user.

A basic difference between 8-bit and 16-bit operation is

that the data is transmitted out of bit 7 of the SPIxSR for

8-bit operation, and data is transmitted out of bit 15 of

the SPIxSR for 16-bit operation. In both modes, data is

shifted into bit 0 of the SPIxSR.

15.1.2

SDOx DISABLE

A control bit, DISSDO, is provided to the SPIxCON reg-

ister to allow the SDOx output to be disabled. This

allows the SPI module to be connected in an input-only

configuration. SDOx can also be used for general

purpose I/O.

Note:

This data sheet summarizes features of

this group of dsPIC30F devices and is not

intended to be a complete reference

source. For more information on the CPU,

peripherals,

descriptions

and

general device functionality, refer to the

“dsPIC30F Family Reference Manual”

(DS70046).

Note:

Both the transmit buffer (SPIxTXB) and

the receive buffer (SPIxRXB) are mapped

to the same register address, SPIxBUF.

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