30F4013 datasheet(54/228 Pages) MICROCHIP

54 / 228 page

dsPIC30F3014/4013

DS70138G-page 54

 2010 Microchip Technology Inc.

FIGURE 7-2:

BLOCK DIAGRAM OF A SHARED PORT STRUCTURE

7.2

Configuring Analog Port Pins

The use of the ADPCFG and TRIS registers control the

operation of the A/D port pins. The port pins that are

desired as analog inputs must have their correspond-

ing TRIS bit set (input). If the TRIS bit is cleared

(output), the digital output level (VOH or VOL) is

converted.

When the PORT register is read, all pins configured as

analog input channels are read as cleared (a low level).

Pins configured as digital inputs will not convert an

analog input. Analog levels on any pin that is defined as

a digital input (including the ANx pins) may cause the

input buffer to consume current that exceeds the

device specifications.

7.2.1

I/O PORT WRITE/READ TIMING

One instruction cycle is required between a port

direction change or port write operation and a read

operation of the same port. Typically, this instruction

would be a NOP.

EXAMPLE 7-1:

PORT WRITE/READ

EXAMPLE

WR LAT +

TRIS Latch

I/O Pad

WR PORT

Data Bus

Data Latch

Read LAT

Read PORT

Read TRIS

WR TRIS

Peripheral Output Data

Peripheral Input Data

I/O Cell

Peripheral Module

Peripheral Output Enable

PIO Module

Output Multiplexers

Input Data

Peripheral Module Enable

Output Enable

Output Data

MOV 0xFF00, W0 ; Configure PORTB<15:8>

; as inputs

MOV W0, TRISB

; and PORTB<7:0> as outputs

NOP

; additional instruction

cycle

BTSS PORTB, #11 ; bit test RB11 and skip if set

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