30F4013 datasheet(61/228 Pages) MICROCHIP

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DS70138G-page 61

dsPIC30F3014/4013

TABLE 8-2:

dsPIC30F4013 INTERRUPT

VECTOR TABLE

8.2

Reset Sequence

A Reset is not a true exception because the interrupt

controller is not involved in the Reset process. The pro-

cessor initializes its registers in response to a Reset

which forces the PC to zero. The processor then begins

program execution at location 0x000000. A GOTO

instruction is stored in the first program memory loca-

tion immediately followed by the address target for the

GOTO

instruction. The processor executes the GOTO to

the specified address and then begins operation at the

specified target (start) address.

8.2.1

RESET SOURCES

In addition to external Reset and Power-on Reset

(POR), these sources of error conditions ‘trap’ to the

Reset vector:

• Watchdog Time-out:

The watchdog has timed out, indicating that the

processor is no longer executing the correct flow

of code.

• Uninitialized W Register Trap:

An attempt to use an uninitialized W register as

an Address Pointer causes a Reset.

• Illegal Instruction Trap:

Attempted execution of any unused opcodes

results in an illegal instruction trap. Note that a

fetch of an illegal instruction does not result in an

illegal instruction trap if that instruction is flushed

prior to execution due to a flow change.

• Brown-out Reset (BOR):

A momentary dip in the power supply to the

device has been detected which may result in

malfunction.

• Trap Lockout:

Occurrence of multiple trap conditions

simultaneously causes a Reset.

Interrupt

Number

Vector

Number

Interrupt Source

Highest Natural Order Priority

INT0 – External Interrupt 0

IC1 – Input Capture 1

OC1 – Output Compare 1

311

T1 – Timer1

IC2 – Input Capture 2

OC2 – Output Compare 2

614

T2 V Timer2

715

T3 – Timer3

SPI1

U1RX – UART1 Receiver

U1TX – UART1 Transmitter

ADC – ADC Convert Done

NVM – NVM Write Complete

SI2C – I2C™ Slave Interrupt

MI2C – I2C Master Interrupt

Input Change Interrupt

INT1 – External Interrupt 1

IC7 – Input Capture 7

IC8 – Input Capture 8

OC3 – Output Compare 3

OC4 – Output Compare 4

T4 – Timer4

T5 – Timer5

INT2 – External Interrupt 2

U2RX – UART2 Receiver

U2TX – UART2 Transmitter

Reserved

C1 – Combined IRQ for CAN1

28-40

36-48

Reserved

DCI – CODEC Transfer Done

LVD – Low-Voltage Detect

43-53

51-61

Reserved

Lowest Natural Order Priority

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