30F4013 datasheet(114/228 Pages) MICROCHIP

114 / 228 page

dsPIC30F3014/4013

DS70138G-page 114

 2010 Microchip Technology Inc.

17.4

Message Reception

17.4.1

RECEIVE BUFFERS

The CAN bus module has 3 receive buffers. However,

one of the receive buffers is always committed to mon-

itoring the bus for incoming messages. This buffer is

called the Message Assembly Buffer (MAB). So there

are 2 receive buffers visible, denoted as RXB0 and

RXB1, that can essentially instantaneously receive a

complete message from the protocol engine.

All messages are assembled by the MAB and are trans-

ferred to the RXBn buffers only if the acceptance filter

criterion are met. When a message is received, the

RXnIF flag (CiINRF<0> or CiINRF<1>) is set. This bit

can only be set by the module when a message is

received. The bit is cleared by the CPU when it has com-

pleted processing the message in the buffer. If the

RXnIE bit (CiINTE<0> or CiINTE<1>) is set, an interrupt

is generated when a message is received.

RXF0 and RXF1 filters with RXM0 mask are associated

with RXB0. The filters RXF2, RXF3, RXF4 and RXF5,

and the mask RXM1 are associated with RXB1.

17.4.2

MESSAGE ACCEPTANCE FILTERS

The message acceptance filters and masks are used to

determine if a message in the message assembly buf-

fer should be loaded into either of the receive buffers.

Once a valid message has been received into the Mes-

sage Assembly Buffer (MAB), the identifier fields of the

message are compared to the filter values. If there is a

match, that message is loaded into the appropriate

receive buffer.

The acceptance filter looks at incoming messages for

the RXIDE bit (CiRXnSID<0>) to determine how to

compare the identifiers. If the RXIDE bit is clear, the

message is a standard frame and only filters with the

EXIDE bit (CiRXFnSID<0>) clear are compared. If the

RXIDE bit is set, the message is an extended frame

and only filters with the EXIDE bit set are compared.

17.4.3

MESSAGE ACCEPTANCE FILTER

MASKS

The mask bits essentially determine which bits to apply

the filter to. If any mask bit is set to a zero, that bit is

automatically accepted regardless of the filter bit.

There are two programmable acceptance filter masks

associated with the receive buffers, one for each buffer.

17.4.4

RECEIVE OVERRUN

An overrun condition occurs when the Message

Assembly Buffer (MAB) has assembled a valid

received message, the message is accepted through

the acceptance filters, and when the receive buffer

associated with the filter has not been designated as

clear of the previous message.

The overrun error flag, RXnOVR (CiINTF<15> or

CiINTF<14>), and the ERRIF bit (CiINTF<5>) are set

and the message in the MAB is discarded.

If the DBEN bit is clear, RXB1 and RXB0 operate inde-

pendently. When this is the case, a message intended

for RXB0 is not diverted into RXB1 if RXB0 contains an

unread message, and the RX0OVR bit is set.

If the DBEN bit is set, the overrun for RXB0 is handled

differently. If a valid message is received for RXB0 and

RXFUL = 1

indicates

that

RXB0

full

and

RXFUL = 0 indicates that RXB1 is empty, the message

for RXB0 is loaded into RXB1. An overrun error is not

generated for RXB0. If a valid message is received for

RXB0 and RXFUL = 1, indicates that both RXB0 and

RXB1 are full, the message is lost and an overrun is

indicated for RXB1.

17.4.5

RECEIVE ERRORS

The CAN module detects the following receive errors:

• Cyclic Redundancy Check (CRC) error

• Bit Stuffing error

• Invalid Message Receive Error

The receive error counter is incremented by one in

case one of these errors occur. The RXWAR bit

(CiINTF<9>) indicates that the receive error counter

has reached the CPU warning limit of 96 and an

interrupt is generated.

17.4.6

RECEIVE INTERRUPTS

Receive interrupts can be divided into 3 major groups,

each including various conditions that generate

interrupts:

• Receive Interrupt:

A message has been successfully received and

loaded into one of the receive buffers. This inter-

rupt is activated immediately after receiving the

End-of-Frame (EOF) field. Reading the RXnIF flag

indicates

which

receive

buffer

caused

the

interrupt.

• Wake-up Interrupt:

The CAN module has woken up from Disable

mode or the device has woken up from Sleep

mode.

30F4013 Datasheet(PDF) 114 Page - Microchip Technology

30F4013 Datasheet(HTML) 114 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL