ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Rev. F

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Page 29 of 64

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March 2008

Synchronous Read/Write—Bus Slave

Use these specifications for bus master accesses of a slave’s IOP

registers or internal memory (in multiprocessor memory space).

The bus master must meet the bus slave timing requirements.

Table 17. Synchronous Read/Write—Bus Slave

5 V and 3.3 V

Unit

Parameter

Min

Max

Timing Requirements

Address, SW Setup Before CLKIN

15 + DT/2

ns

Address, SW Hold After CLKIN

5 + DT/2

ns

RD/WR Low Setup Before CLKIN1

9.5 + 5DT/16

ns

RD/WR Low Hold After CLKIN2

–4 – 5DT/16

8 + 7DT/16

ns

RD/WR Pulse High

3

ns

Data Setup Before WR High

5

ns

Data Hold After WR High

1

ns

Switching Characteristics

Data Delay After CLKIN3

18 + 5DT/16

ns

Data Disable After CLKIN4

0 – DT/8

7 – DT/8

ns

ACK Delay After Address, SW5

9ns

ACK Disable After CLKIN5

–1 – DT/8

6 – DT/8

ns

greater than 19 + 3DT/4, then ACK is valid 14 + DT/4 (max) after CLKIN. A slave that sees an address with an M field match will respond with ACK regardless of the state

Figure 17. Synchronous Read/Write—Bus Slave

CLKIN

ADDRESS

ACK

RD

DATA

(OU T)

WR

WRITE ACCESS

DATA

(IN)

READ ACCESS