ADSP-21062LABZ-160 datasheet(44/64 Pages) AD

44 / 64 page

Rev. F

Page 44 of 64

March 2008

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

Figure 25. Serial Ports

DRIVE EDGE

DRIVE

EDGE

DRIVE

EDGE

TCLK/RCLK

TCLK

(INT)

TCLK/RCLK

TCLK

(EXT)

RCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

DATA RECEIVE— INTERNAL CLOCK

DATA RECEIVE— EXTERNAL CLOCK

RCLK

RFS

DRIVE

EDGE

SAMPLE

EDGE

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

TCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

TCLK

TFS

DRIVE

EDGE

SAMPLE

EDGE

DATA TRANSMIT— INTERNAL CLOCK

DATA TRANSMIT— EXTERNAL CLOCK

NOTE: EITHER THE RISING EDGE OR FALLING EDGE OF RCLK, TCLK CAN BE USED AS THE ACTIVE SAMPLING EDGE.

tDDTTE

tDDTEN

tDDTTI

tDDTIN

tSDRI

tHDRI

tSFSI

tHFSI

tDFSE

tHOFSE

tSCLKIW

tSDRE

tHDRE

tSFSE

tHFSE

tDFSE

tSCLKW

tHOFSE

tDDTI

tHDTI

tSFSI

tHFSI

tSCLKIW

tDFSI

tHOFSI

tDDTE

tHDTE

tSFSE

tHFSE

tDFSE

tSCLKW

tHOFSE

CLKIN

tDPTR

SPORT DISABLE DELAY

FROM INSTRUCTION

TCLK, RCLK

TFS, RFS, DT

TCLK (INT)

RCLK (INT)

SPORT ENABLE AND

THREE-STATE

LATENCY

IS TWO CYCLES

tDCLK

LOW TO HIGH ONLY

tSTFSCK

CLKIN

tHTFSCK

NOTE: APPLIES ONLY TO GATED SERIAL CLOCK MODE WITH

EXTERNAL TFS, AS USED IN THE SERIAL PORT SYSTEM I/O

FOR MESH MULTIPROCESSING.

TFS (EXT)

ADSP-21062LABZ-160 Datasheet(PDF) 44 Page - Analog Devices

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