ADSP-21062LABZ-160 datasheet(46/64 Pages) AD

46 / 64 page

Rev. F

Page 46 of 64

March 2008

ADSP-21060/ADSP-21060L/ADSP-21062/ADSP-21062L/ADSP-21060C/ADSP-21060LC

JTAG Test Access Port and Emulation

For JTAG Test Access Port and Emulation, see Table 36 and

Figure 27.

Table 36. JTAG Test Access Port and Emulation

Parameter

Min

Max

Unit

Timing Requirements

tTCK

TCK Period

tCK

tSTAP

TDI, TMS Setup Before TCK High

tHTAP

TDI, TMS Hold After TCK High

tSSYS

System Inputs Setup Before TCK Low1

7ns

tHSYS

System Inputs Hold After TCK Low1, 2

tTRSTW

TRST Pulse Width

4 tCK

Switching Characteristics

tDTDO

TDO Delay from TCK Low

tDSYS

System Outputs Delay After TCK Low3

18.5

1 System Inputs = DATA63–0, ADDR31–0, RD, WR, ACK, SBTS, HBR, HBG, CS, DMAR1, DMAR2, BR6–1, ID2–0, RPBA, IRQ2–0, FLAG3–0, PA, BRST, DR0, DR1, TCLK0,

TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, EBOOT, LBOOT, BMS, CLKIN, RESET.

2 For ADSP-21060L/ADSP-21060LC/ADSP-21062L, specification is 18.5 ns min.

3 System Outputs = DATA63–0, ADDR31–0, MS3–0, RD, WR, ACK, PAGE, CLKOUT, HBG, REDY, DMAG1, DMAG2, BR6–1, PA, BRST, CIF, FLAG3–0, TIMEXP, DT0,

DT1, TCLK0, TCLK1, RCLK0, RCLK1, TFS0, TFS1, RFS0, RFS1, LxDAT7–0, LxCLK, LxACK, BMS.

Figure 27. JTAG Test Access Port and Emulation

TCK

TMS

TDI

TDO

SYSTEM

INPUTS

SYSTEM

OUTPUTS

tSTAP

tTCK

tHTAP

tDTDO

tSSYS

tHSYS

tDSYS

ADSP-21062LABZ-160 Datasheet(PDF) 46 Page - Analog Devices

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