APW7323KAI-TRG datasheet(15/22 Pages) ANPEC

15 / 22 page

Rev. A.5 - Aug., 2013

APW7323/A

www.anpec.com.tw

Application Information (Cont.)

Output Capacitor Selection (Cont.)

LIM

PEAK

OUT

P-FET

∆I

Layout Considerations

For all switching power supplies, the layout is an impor-

tant step in the design; especially at high peak currents

and switching frequencies. If the layout is not carefully

done, the regulator might show noise problems and duty

cycle jitter.

1. The input capacitor should be placed close to the VIN

and GND. Connect the capacitor and VIN/GND with short

and wide trace without any via holes for good input volt-

age filtering. The distance between VIN/GND to capacitor

less than 2mm respectively is recommended.

2. To minimize copper trace connections that can inject

noise into the system, the inductor should be placed as

close as possible to the LX pin to minimize the noise

coupling into other circuits.

3. The output capacitor should be place closed to VOUT

and GND.

4. Keep the sensitive small signal nodes (FB) away from

switching nodes (LX) on the PCB. Therefore place the

feedback divider and the feedback compensation net-

work close to the IC to avoid switching noise. Connect

the ground of feedback divider directly to the GND pin of

the IC using a dedicated ground trace.

5. A star ground connection or ground plane minimizes

ground shifts and noise is recommended.

Recommended Minimum Footprint

1.27

0.5

3.8

Unit : mm

SOP-8P

1.75mm

Ground plane for

ThermalPAD

ThermalVia diameter

12mil X 5

0.275mm

0.75mm

0.50mm

TDFN3X3 -10

0.30mm

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