MSC1202Y2RHHT datasheet(48/92 Pages) TI

48 / 92 page

MSC1200

MSC1201

MSC1202

SBAS317E − APRIL 2004 − REVISED MAY 2006

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Power Control (PCON)

Reset Value

SFR 87h

SMOD

GF1

GF0

STOP

IDLE

30h

SMOD

Serial Port 0 Baud Rate Doubler Enable. The serial baud rate doubling function for Serial Port 0.

bit 7

0: Serial Port 0 baud rate will be a standard baud rate.

1: Serial Port 0 baud rate will be double that defined by baud rate generation equation.

GF1

General-Purpose User Flag 1. This is a general-purpose flag for software control.

bit 3

GF0

General-Purpose User Flag 0. This is a general-purpose flag for software control.

bit 2

STOP

Stop Mode Select. Setting this bit halts the internal oscillator and blocks external clocks. This bit always reads as 0.

bit 1

Exit with RESET. In this mode, internal peripherals are frozen and I/O pins are held in their current state. The ADC is

frozen, but IDAC and VREF remain active.

IDLE

Idle Mode Select. Setting this bit freezes the CPU, Timer 0 and 1, and the USART; other peripherals remain active.

bit 0

This bit will always be read as a 0. Exit with AIE (A6h) and EWU (C6h) interrupts (refer to Figure 6 for clocks affected

during Idle mode).

Timer/Counter Control (TCON)

Reset Value

SFR 88h

TF1

TR1

TF0

TR0

IE1

IT1

IE0

IT0

00h

TF1

Timer 1 Overflow Flag. This bit indicates when Timer 1 overflows its maximum count as defined by the current mode.

bit 7

This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 1 interrupt service routine.

0: No Timer 1 overflow has been detected.

1: Timer 1 has overflowed its maximum count.

TR1

Timer 1 Run Control. This bit enables/disables the operation of Timer 1. Halting this timer preserves the current

bit 6

count in TH1, TL1.

0: Timer is halted.

1: Timer is enabled.

TF0

Timer 0 Overflow Flag. This bit indicates when Timer 0 overflows its maximum count as defined by the current mode.

bit 5

This bit can be cleared by software and is automatically cleared when the CPU vectors to the Timer 0 interrupt service routine.

0: No Timer 0 overflow has been detected.

1: Timer 0 has overflowed its maximum count.

TR0

Timer 0 Run Control. This bit enables/disables the operation of Timer 0. Halting this timer preserves the current

bit 4

count in TH0, TL0.

0: Timer is halted.

1: Timer is enabled.

IE1

Interrupt 1 Edge Detect. This bit is set when an edge/level of the type defined by IT1 is detected. If IT1 = 1, this bit

bit 3

will remain set until cleared in software or the start of the External Interrupt 1 service routine. If IT1 = 0, this bit will inversely

reflect the state of the INT1 pin.

IT1

Interrupt 1 Type Select. This bit selects whether the INT1 pin will detect edge- or level-triggered interrupts.

bit 2

0: INT1 is level-triggered.

1: INT1 is edge-triggered.

IE0

Interrupt 0 Edge Detect. This bit is set when an edge/level of the type defined by IT0 is detected. If IT0 = 1, this bit

bit 1

will remain set until cleared in software or the start of the External Interrupt 0 service routine. If IT0 = 0, this bit will inversely

reflect the state of the INT0 pin.

IT0

Interrupt 0 Type Select. This bit selects whether the INT0 pin will detect edge- or level-triggered interrupts.

bit 0

0: INT0 is level-triggered.

1: INT0 is edge-triggered.

MSC1202Y2RHHT Datasheet(PDF) 48 Page - Texas Instruments

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