ADC10D040

SNAS149G – OCT 2001 – REVISED MARCH 2013

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FUNCTIONAL DESCRIPTION

Using a subranging architecture, the ADC10D040 achieves 9.4 effective bits over the entire Nyquist band at 40

MSPS while consuming just 267 mW. The use of an internal sample-and-hold amplifier (SHA) not only enables

this sustained dynamic performance, but also lowers the converter's input capacitance and reduces the number

of external components required.

than

output word to indicate a positive full scale.

Both “I” and “Q” channels are sampled simultaneously on the falling edge of the clock input, while the timing of

the data output depends upon the mode of operation.

In the parallel mode, the “I” and “Q” output busses contain the conversion result for their respective inputs. The

a delayed I/Q output signal should be used to latch the output for best, most consistent results.

Data latency in the parallel mode is 2.5 clock cycles. In the multiplexed mode data latency is 2.5 clock cycles for

the “I” channel and 3.0 clock cycles for the “Q” channel. The ADC10D040 will convert as long as the clock signal

is present and the PD and STBY pins are low.

to its Common Mode output voltage.

Applications Information

THE ANALOG SIGNAL INPUTS

Each of the analog inputs of the ADC10D040 consists of a switch (transmission gate) followed by a switched

capacitor amplifier. The capacitance seen at each input pin changes with the clock level, appearing as about 2

pF when the clock is low, and about 5 pF when the clock is high. This switching action causes analog input

current spikes that work with the input source impedance to produce voltage spikes.

The LMH6702 and the CLC428 dual op-amp have been found to be a good amplifiers to drive the ADC10D040

because of their wide bandwidth and low distortion. They also have good Differential Gain and Differential Phase

performance.

Care should be taken to avoid driving the input beyond the supply rails, even momentarily, as during power-up.

The ADC10D040 is designed for differential input signals for best performance. With a 1.4V reference and the

signals, the input common mode is expected to be about 1.5V, but the inputs are not sensitive to the common-

degradation, as long as the signal swing at the individual input pins is no more than 300 mV beyond the supply

rails.

Single-ended drive is not recommended as it can result in degraded dynamic performance and faulty operation. If

single-ended input drive is absolutely required, it is recommended that a sample rate above 30 MSPS be used. If

the desired sample rate is lower than this, operate the ADC10D040 at a multiple of the desired rate and decimate

the output (use every "nth" sample).

For single-ended drive, operate the ADC10D040 with the GAIN pin at a logic low, connect one pin of the input

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