| Electronic Components Datasheet Search |
|
ADC10D040CIVS/NOPB Datasheet(PDF) 27 Page - Texas Instruments |
|
|
|
|||||||||||||||||||||||||||||
ADC10D040CIVS/NOPB Datasheet(HTML) 27 Page - Texas Instruments |
|
27 / 32 page ![]() ADC10D040 www.ti.com SNAS149G – OCT 2001 – REVISED MARCH 2013 DYNAMIC PERFORMANCE The ADC10D040 is a.c. tested and its dynamic performance is specified. To meet the published specifications, the clock source driving the CLK input must be free of jitter. For best dynamic performance, isolating the ADC clock from any digital circuitry should be done with adequate buffers, as with a clock tree. See Figure 39. Figure 39. Isolating the ADC Clock from Digital Circuitry COMMON APPLICATION PITFALLS Driving the inputs (analog or digital) beyond the power supply rails. For proper operation, no input should go more than 300 mV beyond the supply pins, Exceeding these limits on even a transient basis can cause faulty or erratic operation. It is not uncommon for high speed digital circuits (e.g., 74F and 74AC devices) to exhibit overshoot and undershoot that goes a few hundred millivolts beyond the supply rails. A resistor of 50 Ω to 100Ω in series with the offending digital input, close to the source, will usually eliminate the problem. Care should be taken not to overdrive the inputs of the ADC10D040 (or any device) with a device that is powered from supplies outside the range of the ADC10D040 supply. Such practice may lead to conversion inaccuracies and even to device damage. Attempting to drive a high capacitance digital data bus. The more capacitance the output drivers have to charge for each conversion, the more instantaneous digital current is required from VDR and DR GND. These large charging current spikes can couple into the analog section, degrading dynamic performance. Adequate bypassing and attention to board layout will reduce this problem. Buffering the digital data outputs (with a 74ACTQ841, for example) may be necessary if the data bus to be driven is heavily loaded. Dynamic performance can also be improved by adding series resistors of 47 Ω to 56Ω at each digital output, close to the ADC output pins. Using a clock source with excessive jitter. This will cause the sampling interval to vary, causing excessive output noise and a reduction in SNR and SINAD performance. The use of simple gates with RC timing as a clock source is generally inadequate. Using the same voltage source for VD and external digital logic. As mentioned in POWER SUPPLY CONSIDERATIONS, VD should use the same power source used by VA and other analog components, but should be decoupled from VA. Copyright © 2001–2013, Texas Instruments Incorporated Submit Documentation Feedback 27 Product Folder Links: ADC10D040 |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |