ADC10D040CIVSSLASHNOPB datasheet(8/32 Pages) TI1

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ADC10D040

SNAS149G – OCT 2001 – REVISED MARCH 2013

www.ti.com

Converter Electrical Characteristics (continued)

The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5 VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 3.3V, VIN

(a.c. coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.

Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C

(1)

Units

Symbol

Parameter

Conditions

Typical(2)

Limits(3)

(Limits)

PD = LOW, STBY = LOW, d.c. input

267

305

mW (max)

PD = LOW, STBY = LOW, 1 MHz Input

270

Power Consumption

PD = LOW, STBY = HIGH

PD = HIGH, STBY = LOW or HIGH

0.6

Change in Full Scale with 3.0V to 3.6V Supply

PSRR1

Power Supply Rejection Ratio

Change

Rejection at output with 10.3 MHz, 250 mVP-P

PSRR2

Power Supply Rejection Ratio

Riding on VA and VD

AC Electrical Characteristics

OS = Low (Multiplexed Mode)

The following specifications apply for VA = VD = +3.3 VDC, VDR = +2.5VDC, VREF = 1.4 VDC, GAIN = OF = 0V, OS = 0V, VIN (a.c.

coupled) = FSR = 1.4 VP-P, CL = 15 pF, fCLK = 40 MHz, 50% Duty Cycle, RS = 50Ω, trc = tfc < 4 ns, NOT offset corrected.

Boldface limits apply for TA = TMIN to TMAX: all other limits TA = 25°C

(1)

Units

Symbol

Parameter

Conditions

Typical(2)

Limits(3)

(Limits)

fCLK1

Maximum Clock Frequency

MHz (min)

fCLK2

Minimum Clock Frequency

MHz

% (min)

Duty Cycle

% (max)

Clock

I Data

2.5

Cycles

Pipeline Delay (Latency)

Clock

Q Data

3.0

Cycles

tr, tf

Output Rise and Fall Times

tOC

Offset Correction Pulse Width

ns (min)

tOD

Output Delay from CLK Edge to Data Valid

ns (max)

tDIQ

I/Q Output Delay

tSKEW

I/Q to Data Skew

±200

tAD

Sampling (Aperture) Delay

2.2

tAJ

Aperture Jitter

<10

ps (rms)

tVALID

Data Valid Time

7.5

Differential VIN step from

Overrange Recovery Time

1.5V to 0V

(1)

The inputs are protected as shown below. Input voltage magnitude up to 300 mV beyond the supply rails will not damage this device.

However, errors in the A/D conversion can occur if the input goes beyond the limits given in these tables.

(2)

Typical figures are at TJ = 25°C, and represent most likely parametric norms.

(3)

Test limits are specified to TI's AOQL (Average Outgoing Quality Level). Performance is specified only at VREF = 1.4V and a clock duty

cycle of 50%. The limits for VREF and clock duty cycle specify the range over which reasonable performance is expected. Tests are

performed and limits specified with clock low and high levels of 0.3V and VD−0.3V, respectively.

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