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AN4243 Datasheet(PDF) 16 Page - STMicroelectronics |
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AN4243 Datasheet(HTML) 16 Page - STMicroelectronics |
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16 / 29 page ![]() Designing an application with the L6230 AN4243 16/29 Doc ID 024199 Rev 1 Figure 13. L6230 overcurrent detection simplified circuitry This sensed current is compared to an internally-generated reference to detect an overcurrent condition. An internal open-drain MOSFET turns on when the sum of the currents in the bridge 1, the bridge 2 or the bridge 3 reaches the threshold (2.8 A typical value); the open-drain is available at the DIAG-EN pin for diagnostic purposes and to ensure an overcurrent protection, connecting an RC network (see Figure 13). Figure 14 shows the device operating in overcurrent condition. When an overcurrent is detected the internal open-drain MOSFET pulls the DIAG-EN pin to GND, switching off all 6 power DMOS of the device and allowing the current to decay. Under a persistent overcurrent condition, like a short to ground or a short between two output pins, the external RC network on the EN pin (see Figure 13) reduces the RMS value of the output current by imposing a fixed disable time after each overcurrent occurrence. The values of REN and CEN are selected to ensure proper operation of the device under a short-circuit condition. When the current flowing through the high-side DMOS reaches the OCD threshold (2.8 A typ.), after an internal propagation delay (tOCD(ON)) the open-drain starts discharging CEN. When the DIAG-EN pin voltage falls below the turn-off threshold (VTH(OFF)) all the Power DMOS turn off after the internal propagation delay (tD(OFF)EN). The current begins decaying as it circulates through the freewheeling diodes. Since the DMOS are off, there is no current flowing through them and no current to sense so the OCD circuit, after a short delay (tOCD(OFF)), switches the internal open-drain device off, and REN can charge CEN. When the voltage at DIAG-EN pin reaches the turn-on threshold (VTH(ON)), after the tD(ON)EN delay, the DMOS turn on and the current restarts. Even if the maximum output current can be very high, the external RC network provides a disable time (tDISABLE) to ensure a safe RMS value (see Figure 14). + OVER TEMPERATURE IREF I1+I2 / n I1 / n HIGH SIDE DMOS POWER SENSE 1 cell POWER SENSE 1 cell POWER SENSE 1 cell POWER DMOS n cells POWER DMOS n cells POWER DMOS n cells OUT1 OUT2 VSA OUT3 VSB I1 I2 I3 I2/ n OCD COMPARATOR TO GATE LOGIC INTERNAL OPEN-DRAIN RDS(ON) 40 Ω TYP. CEN REN DIAG-EN VDD μC or LOGIC I3/ n + I3 AM16575v1 |
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