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PD46185092B Datasheet(PDF) 12 Page - Renesas Technology Corp

Part # PD46185092B
Description  18M-BIT QDRTM II SRAM 2-WORD BURST OPERATION
PDF  36 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

PD46185092B Datasheet(HTML) 12 Page - Renesas Technology Corp

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μPD46185092B, μPD46185182B, μPD46185362B
R10DS0112EJ0200 Rev.2.00
Page 12 of 35
Nov 09, 2012
Bus Cycle State Diagram
READ DOUBLE
WRITE DOUBLE
AT K#
Power UP
Always
Supply voltage
provided
LOAD NEW
READ ADDRESS
READ PORT NOP
R_Init = 0
WRITE PORT NOP
LOAD NEW
WRITE ADDRESS
AT K#
Always
W# = LOW
Supply voltage
provided
W# = LOW
W# = HIGH
W# = HIGH
R# = LOW
R# = LOW
R# = HIGH
R# = HIGH
Remarks 1. The address is concatenated with 1 additional internal LSB to facilitate burst operation.
The address order is always fixed as: xxx...xxx+0, xxx...xxx+1.
Bus cycle is terminated at the end of this sequence (burst count = 2).
2. Read and write state machines can be active simultaneously.
3. State machine control timing sequence is controlled by K.



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