PD46185092B_15 datasheet(27/36 Pages) RENESAS

27 / 36 page

μPD46185092B, μPD46185182B, μPD46185362B

R10DS0112EJ0200 Rev.2.00

Page 27 of 35

Nov 09, 2012

JTAG Instructions

Instructions

Description

EXTEST

The EXTEST instruction allows circuitry external to the component package to be tested.

Boundary-scan register cells at output pins are used to apply test vectors, while those at

input pins capture test results. Typically, the first test vector to be applied using the

EXTEST instruction will be shifted into the boundary scan register using the PRELOAD

instruction. Thus, during the update-IR state of EXTEST, the output drive is turned on and

the PRELOAD data is driven onto the output pins.

IDCODE

The IDCODE instruction causes the ID ROM to be loaded into the ID register when the

controller is in capture-DR mode and places the ID register between the TDI and TDO pins

in shift-DR mode. The IDCODE instruction is the default instruction loaded in at power up

and any time the controller is placed in the test-logic-reset state.

BYPASS

When the BYPASS instruction is loaded in the instruction register, the bypass register is

placed between TDI and TDO. This occurs when the TAP controller is moved to the shift-

DR state. This allows the board level scan path to be shortened to facilitate testing of other

devices in the scan path.

SAMPLE / PRELOAD SAMPLE / PRELOAD is a Standard 1149.1 mandatory public instruction.

When the

SAMPLE / PRELOAD instruction is loaded in the instruction register, moving the TAP

controller into the capture-DR state loads the data in the RAMs input and Q pins into the

boundary scan register. Because the RAM clock(s) are independent from the TAP clock

(TCK) it is possible for the TAP to attempt to capture the I/O ring contents while the input

buffers are in transition (i.e., in a metastable state). Although allowing the TAP to sample

metastable input will not harm the device, repeatable results cannot be expected. RAM

input signals must be stabilized for long enough to meet the TAPs input data capture setup

plus hold time (tCS plus tCH). The RAMs clock inputs need not be paused for any other

TAP operation except capturing the I/O ring contents into the boundary scan register.

Moving the controller to shift-DR state then places the boundary scan register between the

TDI and TDO pins.

SAMPLE-Z

If the SAMPLE-Z instruction is loaded in the instruction register, all RAM Q pins are forced

to an inactive drive state (high impedance) and the boundary register is connected between

TDI and TDO when the TAP controller is moved to the shift-DR state.

JTAG Instruction Coding

IR2

IR1

IR0

Instruction

Note

EXTEST

IDCODE

SAMPLE-Z

RESERVED

SAMPLE / PRELOAD

RESERVED

BYPASS

Notes 1. TRISTATE all Q pins and CAPTURE the pad values into a SERIAL SCAN LATCH.

2. Do not use this instruction code because the vendor uses it to evaluate this product.

PD46185092B Datasheet(PDF) 27 Page - Renesas Technology Corp

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