PD46185092B_15 datasheet(29/36 Pages) RENESAS

29 / 36 page

μPD46185092B, μPD46185182B, μPD46185362B

R10DS0112EJ0200 Rev.2.00

Page 29 of 35

Nov 09, 2012

Boundary Scan Register Status of Output Pins CQ, CQ# and Q

Instructions

SRAM Status

Boundary Scan Register Status

Note

CQ,CQ#

EXTEST

READ (Low-Z)

Pad

NOP (High-Z)

Pad

IDCODE

READ (Low-Z)

–

No definition

NOP (High-Z)

–

SAMPLE-Z

READ (Low-Z)

Pad

NOP (High-Z)

Pad

SAMPLE

READ (Low-Z)

Internal

NOP (High-Z)

Internal

Pad

BYPASS

READ (Low-Z)

–

No definition

NOP (High-Z)

–

Remark The Boundary Scan Register statuses during execution each

instruction vary according to the instruction code and SRAM

operation mode.

There are two statuses:

Pad

: Contents of the output pin (QDR Pad) are captured

in the “CAPTURE Register” in the Boundary Scan

Internal : Contents of the SRAM internal output “SRAM

Output” are captured in the “CAPTURE Register”

in the Boundary Scan Register.

Pad

Internal

SRAM

Output

Driver

Update

QDR

Pad

High-Z

JTAG ctrl

CAPTURE

SRAM

Output

Boundary Scan

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