μPD46185092B, μPD46185182B, μPD46185362B

R10DS0112EJ0200 Rev.2.00

Page 19 of 35

Nov 09, 2012

Notes 1. When debugging the system or board, these products can operate at a clock frequency slower than TKHKH

(MAX.) without the PLL circuit being used, if DLL# = LOW. Read latency (RL) is changed to 1.0 clock

cycle in this operation. The AC/DC characteristics cannot be guaranteed, however.

2. Clock phase jitter is the variance from clock rising edge to the next expected clock rising edge. TKC var

(MAX.) indicates a peak-to-peak value.

It is recommended that the device is kept NOP (R# = W# = HIGH) during these cycles.

4. K input is monitored for this operation. See below for the timing.

K

K

TKC reset

or

TKC reset

5. Guaranteed by design.

6. Echo clock is very tightly controlled to data valid / data hold. By design, there is a

± 0.1 ns variation from

echo clock to data. The data sheet parameters reflect tester guardbands and test setup variations.

7. This is a synchronous device. All addresses, data and control lines must meet the specified setup

and hold times for all latching clock edges.

Remarks 1. This parameter is sampled.

2. Test conditions as specified with the output loading as shown in AC Test Conditions unless otherwise

noted.

3. Control input signals may not be operated with pulse widths less than TKHKL (MIN.).

4. If C, C# are tied HIGH, K, K# become the references for C, C# timing parameters.