μPD46185092B, μPD46185182B, μPD46185362B

R10DS0112EJ0200 Rev.2.00

Page 20 of 35

Nov 09, 2012

Read and Write Timing

K

Address

Data in

K#

24

68

10

1

3

579

TKHK#H TK#HKH

C

C#

TKHCH

NOP

READ

READ

READ

WRITE

WRITE

WRITE

TKHKL

TKLKH

Q00

Q20

Data out

Q01

Q21

Q41

Q40

R#

W#

A1

A3

A2

A4

A6

A5

A0

D11

D31

D30

D50

D61

D51

D10

D60

TKHKL

TKLKH

TKHK#H

TK#HKH

TKHKH

TCHQX1

TCHQV

TCHQX

TCHQX

TCHQZ

TDVKH TKHDX

TDVKH TKHDX

TKHKH

TIVKH

TKHIX

TAVKH

TKHAX

TAVKH

TKHAX

NOP

WRITE

CQ

CQ#

TCHQV

TCHCQV

TCHCQX

TCHCQV

TKHCH

TCHCQX

TCQHQV

TCQHQX

TCQ#HCQH

TCQHCQ#H

Remarks 1. Q00 refers to output from address A0+0.

Q01 refers to output from the next internal burst address following A0,i.e.,A0+1.

2. Outputs are disabled (high impedance) 2.5 clock cycles after the last READ (R# = LOW) is input in the

sequences of [READ/WRITE]-[NOP/WRITE], [READ/WRITE]-[NOP/NOP], [READ/NOP]-

[NOP/WRITE] and [READ/NOP] -[NOP/NOP].

3. In this example, if address A0 = A1, data Q00 = D10, Q01 = D11.

Write data is forwarded immediately as read results.