PD46185092B_15 datasheet(28/36 Pages) RENESAS

28 / 36 page

μPD46185092B, μPD46185182B, μPD46185362B

R10DS0112EJ0200 Rev.2.00

Page 28 of 35

Nov 09, 2012

Output Pin States of CQ, CQ# and Q

Instructions

Control-Register Status

Output Pin Status

CQ,CQ#

EXTEST

Update

High-Z

Update

IDCODE

SRAM

SAMPLE-Z

High-Z

SAMPLE

SRAM

BYPASS

SRAM

Remark The output pin statuses during each instruction vary according

to the Control-Register status (value of Boundary Scan

There are three statuses:

Update : Contents of the “Update Register” are output to

the output pin (QDR Pad).

SRAM : Contents of the SRAM internal output “SRAM

Output” are output to the output pin (QDR Pad).

High-Z : The output pin (QDR Pad) becomes high

impedance by controlling of the “High-Z JTAG

ctrl”.

The Control-Register status is set during Update-DR at the

EXTEST or SAMPLE instruction.

SRAM

CAPTURE

Boundary Scan

Update

QDR

Pad

SRAM

Output

Driver

High-Z

JTAG ctrl

High-Z

Update

SRAM

Output

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