TAS5760LDAPR datasheet(29/77 Pages) TI1

29 / 77 page

TAS5760L

www.ti.com

SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015

RL is the load resistance.

VP is the peak amplitude achievable when the soft clipper circuit is active (As mentioned previously, VP = [4 x

VSFT_CLIP], provided that [4 x VSFT_CLIP] < PVDD.)

POUT (10%THD) ≈ 1.25 × POUT (unclipped)

If the PVDD level is below (4 x VSFT_CLIP) clipping will occur due to clipping at PVDD before the clipping due to

the soft clipper circuit becomes active.

Table 4. Soft Clipper Example

Resistor to GND

PVDD [V]

SFT_CLIP Pin Voltage [V]

Resistor to GVDD [k

Ω]

Output Voltage [Vrms]

Ω]

GVDD

(Open)

10.33

2.25

9.00

1.5

6.30

9.4.1.4 Speaker Amplifier Switching Frequency Select (FREQ/SDA Pin)

In Hardware Control mode, the PWM switching frequency of the TAS5760L is configurable via the FREQ/SDA

pin. When connected to the system ground, the pin sets the output switching frequency to 16 × fS. When

connected to DVDD through a pull-up resistor, as shown in the Typical Application Circuits, the pin sets the

output switching frequency to 8 × fS. More switching frequencies are available when the TAS5760L is used in

Software Control Mode.

9.4.1.5 Parallel Bridge Tied Load Mode Select (PBTL/SCL Pin)

The TAS5760L can be configured to drive a single speaker with the two output channels connected in parallel.

This mode of operation is called Parallel Bridge Tied Load (PBTL) mode. This mode of operation effectively

reduces the output impedance of the amplifier in half, which in turn reduces the power dissipated in the device

due to conduction losses through the output FETs. Additionally, since the output channels are working in parallel,

it also doubles the amount of current the speaker amplifier can source before hitting the over-current error

threshold.

The device can be placed operated in PBTL mode in either Hardware Control Mode or in Software Control Mode,

via the I²C Control Port. For instructions on placing the device in PBTL via the I²C Control Port, see Software

Control Mode.

To place the TAS5760L into PBTL Mode when operating in Hardware Control Mode, the PBTL/SCL pin should

be pulled HIGH (that is, connected to the DVDD supply through a pull-up resistor). If the device is to operate in

BTL mode instead, the PBTL/SCL pin should be pulled LOW, that is connected to the system supply ground.

When operated in PBTL mode, the output pins should be connected as shown in the Typical Application Circuit

Diagrams.

In PBTL mode, the amplifier selects its source signal from the right channel of the stereo signal presented on the

SDIN line of the Serial Audio Port. To select the right channel of the stereo signal, the LRCK can be inverted in

the processor that is sending the serial audio data to the TAS5760L.

9.4.1.6 Speaker Amplifier Sleep Enable (SPK_SLEEP/ADR Pin)

In Hardware Control mode, pulling the SPK_SLEEP/ADR pin HIGH gracefully transitions the switching of the

output devices to a non-switching state or "High-Z" state. This mode of operation is similar to mute in that no

audio is present on the outputs of the device. However, unlike the 50/50 mute available in the I²C Control Port,

sleep mode saves quiescent power dissipation by stopping the speaker amplifier output transitors from switching.

This mode of operation saves quiescent current operation but keeps signal path blocks active so that normal

operation can resume more quickly than if the device were placed into shutdown. It is recommended to place the

device into sleep mode before stopping the audio signal coming in on the SDIN line or before bringing down the

power supplies connected to the TAS5760L in order to avoid audible artifacts.

Submit Documentation Feedback

Product Folder Links: TAS5760L

TAS5760LDAPR Datasheet(PDF) 29 Page - Texas Instruments

TAS5760LDAPR Datasheet(HTML) 29 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77

Datasheet Download

Link URL