TAS5760LDAPR datasheet(49/77 Pages) TI1

49 / 77 page

TAS5760L

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SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015

10.2.4.2.2

Shutdown Procedures- Hardware Control Mode

1. The device is in normal operation

2. Pull SPK_SLEEP/ADR HIGH

3. Pull SPK_SD LOW

4. The clocks can now be stopped and the power supplies brought down

5. The device is now fully shutdown and powered off

10.2.4.2.3

Digital I/O Connectivity

The digital I/O lines of the TAS5760L are described in previous sections. As discussed, whenever a static digital

pin (that is a pin that is hardwired to be HIGH or LOW) is required to be pulled HIGH, it should be connected to

DVDD through a pullup resistor in order to control the slew rate of the voltage presented to the digital I/O pins. It

is not, however, necessary to have a separate pullup resistor for each static digital I/O line. Instead, a single

resistor can be used to tie all static I/O lines HIGH to reduce BOM count. For instance, if Software Control Mode

is desired both the GAIN[1:0] and the PBTL/SCL pins can both be pulled HIGH through a single pullup resistor.

10.2.4.3 Application Curve

Table 16. Relevant Performance Plots

PLOT TITLE

PLOT NUMBER

Figure 32. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W

G032

Figure 34. Idle Channel Noise vs PVDD

G034

Figure 29. THD+N vs Output Power With PVDD = 12 V With 1 kHz Sine Input

G035

Figure 37. Efficiency vs Output Power

G038

Figure 2. THD+N vs Frequency With PVDD = 12 V, POSPK = 1 W

G004

Figure 17. Idle Channel Noise vs PVDD

G007

Figure 35. THD+N vs Output Power With PVDD = 12 V

G011

Figure 7. Efficiency vs Output Power

G015

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