TAS5760LDAPR datasheet(30/77 Pages) TI1

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Digital to PWM

Conversion

Digital

Boost

Volume

Control

Full Bridge

Power Stage

Serial

Audio

Port

Full Bridge

Power Stage

Gate

Drives

Gate

Drives

Digital

Clipper

Closed Loop Class D Amplifier

Digital Gain

(GDIG)

Analog Gain

(GANA)

011010..

Serial

Audio In

PWM

Audio Out

HPF

Interpolation

Filter

SFT_CLIP

1 2 3 4 5 6

TAS5760L

SLOS782B – JULY 2013 – REVISED SEPTEMBER 2015

www.ti.com

9.4.1.7 Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)

In Hardware Control Mode, a combination of digital gain and analog gain is used to provide the overall gain of

the speaker amplifier. The decode of the two pins "SPK_GAIN1" and "SPK_GAIN0" sets the gain of the speaker

amplifier. Additionally, pulling both of the SPK_SPK_GAIN[1:0] pins HIGH places the device into software control

mode.

As seen in Figure 42, the audio path of the TAS5760L consists of a digital audio input port, a digital audio path, a

digital to PWM converter (DPC), a gate driver stage, a Class D power stage, and a feedback loop which feeds

the output information back into the DPC block to correct for distortion sensed on the output pins. The total

amplifier gain is comprised of digital gain, shown as GDIG in the digital audio path and the analog gain from the

input of the analog modulator GANA to the output of the speaker amplifier power stage.

Figure 42. Speaker Amplifier Gain Select (SPK_GAIN [1:0] Pins)

As shown in Figure 42, the first gain stage for the speaker amplifier is present in the digital audio path. It consists

of the volume control and the digital boost block. The volume control is set to 0dB by default and, in Hardware

Control mode, it does not change. For all settings of the SPK_GAIN[1:0] pins, the digital boost block remains at

+6 dB as analog gain block is transitioned through 19.2, 22.6, and 25 dBV.

The gain configurations provided in Hardware Control mode were chosen to align with popular power supply

levels found in many consumer electronics and to balance the trade-off between maximum power output before

clipping and noise performance. These gain settings ensure that the output signal can be driven into clipping at

those popular PVDD levels. If the power level required is lower than that which is possible with the PVDD level, a

lower gain setting can be used. Additionally, if clipping at a level lower than the PVDD supply is desired, the

digital clipper or soft clipper can be used.

The values of GDIG and GANA for each of the SPK_GAIN[1:0] settings are shown in the table below. Additionally,

the recommended PVDD level for each gain setting, along with the typical unclipped peak to peak output voltage

swing for a 0dBFS input signal is provided. The peak voltage levels in the table below should only be used to

understand the peak target output voltage swing of the amplifier if it had not been limited by clipping at the PVDD

rail.

Table 5. Gain Structure for Hardware Control Mode

Digital

Recommended

A_GAIN

VPk Acheivable Voltage Swing

PVDD Level

Boost

SPK_GAIN[1:0] Pins Setting

[dBV]

(If output is not clipped at PVDD)

[dB]

19.2

12.90

22.6

19.08

This setting is not

recommended for

This setting is not recommended for voltages

voltages supported

supported by the TAS5760L

by the TAS5760L

(Gain is controlled via I²C Port)

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