MEC1322 datasheet(205/456 Pages) MICROCHIP

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 2014 - 2015 Microchip Technology Inc.

DS00001719D-page 205

MEC1322

GIRQx Interrupt Result

Bits D30 down to D0 are defined in the following subsections reflect the state of the GIRQx interrupt source after the

enable bit. The GIRQx result bits are OR’d together to generate the IRQx vector.

Bit D31

Bit D31 is hard-coded to ‘1’.

GIRQx Enable Clear[31:0]

Each GIRQx bit can be individually disabled to assert an interrupt event.

0= Writing a zero has no effect.

1= Writing a one will disable respective GIRQx.

Reading always returns the current value of the GIRQx ENABLE bit. The state of the GIRQx ENABLE bit is determined

by the corresponding GIRQx Enable Set bit and the GIRQx Enable Clear bit. (0=disabled, 1-enabled)

15.9.1

GIRQ8

TABLE 15-9:

GIRQX RESULT REGISTER

Offset

32-bit

EC Size

POWER

VCC1

8000_0000h

VCC1_RESET

Default

BIT

D31

D30

D29

• • •

TYPE

BIT NAME

‘1’

See Tables in the following subsections

TABLE 15-10: GIRQX ENABLE CLEAR REGISTER

Offset

32-bit

Size

POWER

VCC1

0000_0000h

VCC1_RESET

Default

BIT

D31

D30

D29

• • •

TYPE

R/WC except for reserved bits, which are R

BIT NAME

Reserved

See Tables in the following subsections

TABLE 15-11: BIT DEFINITIONS FOR GIRQ8 SOURCE, ENABLE, AND RESULT REGISTERS

Bit

Block Instance

Name

Source Name

Wake

Source Description

[7:0]

GPIO[147:140]

GPIO_Event

Bits[0:7] are controlled by the GPIO_Events gener-

ated by GPIO140 through GPIO147, respectively.

The GPIO Interface can generate an interrupt source

event on a high level, low level, rising edge and fall-

ing edge, as configured by the Interrupt Detection

(int_det) bits in the Pin Control Register associated

with the GPIO signal function.

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