MEC1322 datasheet(87/456 Pages) MICROCHIP

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DS00001719D-page 87

MEC1322

5.8.4.6

AC/DC Specification Issue

All Serial IRQ agents must drive/sample SERIRQ synchronously related to the rising edge of LCLK. The SERIRQ pin

uses the electrical specification of the PCI bus. Electrical parameters will follow the PCI Local Bus Specification, Rev.

2.2 definition of “sustained tri-state.”

5.8.4.7

Reset and Initialization

The SERIRQ bus uses LRESET# as its reset signal and follows the PCI bus reset mechanism. The SERIRQ pin is tri-

stated by all agents while LRESET# is active. With reset, SERIRQ slaves and bridges are put into the (continuous) Idle

mode. The host controller is responsible for starting the initial SERIRQ cycle to collect system’s IRQ/Data default values.

The system then follows with the Continuous/Quiet mode protocol (Stop Frame pulse width) for subsequent SERIRQ

cycles. It is the host controller’s responsibility to provide the default values to the 8259’s and other system logic before

the first SERIRQ cycle is performed. For SERIRQ system suspend, insertion, or removal application, the host controller

should be programmed into Continuous (IDLE) mode first. This is to ensure the SERIRQ bus is in Idle state before the

system configuration changes.

5.8.4.8

SERIRQ Interrupts

The LPC Controller routes Logical Device interrupts onto SIRQ stream frames IRQ[0:15]. Routing is controlled by the

SIRQ Interrupt Configuration Registers. There is one SIRQ Interrupt Configuration Register for each accessible SIRQ

Frame (IRQ); all 16 registers are listed in Table 5-15, "SIRQ Interrupt Configuration Register Map".

The format for each SIRQ Interrupt Configuration Register is described in Section 5.9.2.1, "SIRQ Configuration Register

Format," on page 90. Each Logical Device can have up to two LPC SERIRQ interrupts. When the device is polled by

the host, each SIRQ frame routes the level of the Logical Device interrupt (selected by the corresponding SIRQ Interrupt

Configuration Register) to the SIRQ stream.

5.8.4.9

SERIRQ Routing

Each SIRQ Interrupt Configuration Register controls a series of multiplexers which route to a single Logical Device inter-

rupt as illustrated in FIGURE 5-6: SIRQ Routing Internal Logical Devices on page 88. The following table defines the

Serial IRQ routing for each logical device implemented in the chip.

TABLE 5-12:

LOGICAL DEVICE SIRQ ROUTING

SIRQ Interrupt Configuration

Logical Device Interrupt Source

SELECT

DEVICE

FRAME

Logical Device

(Block Instance -

Note 1:)

Interrupt Source

EMI

EC-to-Host

EMI

Host Event

8042 Keyboard Controller

KIRQ

8042 Keyboard Controller

MIRQ

ACPI EC0

EC_OBF

ACPI EC1

EC_OBF

ACPI PM1

N/A

Legacy Port92/GateA20

N/A

UART 0

UART

Mailbox

MBX_Host SIRQ

Mailbox

MBX_Host_SMI

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