MEC1322 datasheet(85/456 Pages) MICROCHIP

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DS00001719D-page 85

MEC1322

FIGURE 5-5:

SERIAL INTERRUPT WAVEFORM “STOP FRAME”

Stop pulse is two clocks wide for Quiet mode, three clocks wide for Continuous mode.

There may be none, one, or more Idle states during the Stop Frame.

The next SERIRQ cycle’s Start Frame pulse may or may not start immediately after the turn-around clock of the Stop

Frame.

5.8.4.3

SERIRQ Cycle Control

SERIRQ START FRAME

There are two modes of operation for the SERIRQ Start Frame.

Quiet (Active) Mode

Any device may initiate a Start Frame by driving the SERIRQ low for one clock, while the SERIRQ is Idle. After driving

low for one clock, the SERIRQ must immediately be tri-stated without at any time driving high. A Start Frame may not

be initiated while the SERIRQ is active. The SERIRQ is Idle between Stop and Start Frames. The SERIRQ is active

between Start and Stop Frames. This mode of operation allows the SERIRQ to be Idle when there are no IRQ/Data

transitions which should be most of the time.

Once a Start Frame has been initiated, the host controller will take over driving the SERIRQ low in the next clock and

will continue driving the SERIRQ low for a programmable period of three to seven clocks. This makes a total low pulse

width of four to eight clocks. Finally, the host controller will drive the SERIRQ back high for one clock then tri-state.

Any SERIRQ Device which detects any transition on an IRQ/Data line for which it is responsible must initiate a Start

Frame in order to update the host controller unless the SERIRQ is already in an SERIRQ Cycle and the IRQ/Data tran-

sition can be delivered in that SERIRQ Cycle.

Continuous (Idle) Mode

Only the Host controller can initiate a Start Frame to update IRQ/Data line information. All other SERIRQ agents become

passive and may not initiate a Start Frame. SERIRQ will be driven low for four to eight clocks by host controller. This

mode has two functions. It can be used to stop or idle the SERIRQ or the host controller can operate SERIRQ in a con-

tinuous mode by initiating a Start Frame at the end of every Stop Frame.

An SERIRQ mode transition can only occur during the Stop Frame. Upon reset, SERIRQ bus is defaulted to continuous

mode, therefore only the host controller can initiate the first Start Frame. Slaves must continuously sample the Stop

Frames pulse width to determine the next SERIRQ Cycle’s mode.

SERIRQ DATA FRAME

Once a Start Frame has been initiated, the LPC Controller will watch for the rising edge of the Start Pulse and start count-

ing IRQ/Data Frames from there. Each IRQ/Data Frame is three clocks: Sample phase, Recovery phase, and Turn-

around phase. During the sample phase, the LPC Controller must drive the SERIRQ (SIRQ pin) low, if and only if, its

last detected IRQ/Data value was low. If its detected IRQ/Data value is high, SERIRQ must be left tri-stated. During the

recovery phase, the LPC Controller must drive the SERIRQ high, if and only if, it had driven the SERIRQ low during the

previous sample phase. During the turn-around phase, the controller must tri-state the SERIRQ. The device drives the

SERIRQ line low at the appropriate sample point if its associated IRQ/Data line is low, regardless of which device initi-

ated the start frame.

H=Host Control

R=Recovery

T=Turn-around

S=Sample

I= Idle

SERIRQ

LCLK

Host Controller

IRQ15

Driver

None

IRQ14

IRQ15

IOCHCK#

None

STOP

STOP FRAME

START

NEXT CYCLE

FRAME

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