MEC1322 datasheet(55/456 Pages) MICROCHIP

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DS00001719D-page 55

MEC1322

3.8

EC-Only Registers

Note 3-9

The Base Address indicates where the first register can be accessed in a particular address space

for a block instance.

3.9

Sleep Enable and Clock Required Registers

The following are the Sleep Enable and Clock Required registers for the MEC1322.

3.9.1

CHIP SLEEP ENABLE REGISTER (CHIP_SLP_EN)

TABLE 3-8:

EC-ONLY REGISTER BASE ADDRESS TABLE

Block Instance

Instance

Number

Host

Address Space

Base Address (Note 3-9)

PCR

32-bit internal

address space

4008_0100h

TABLE 3-9:

POWER, CLOCKS AND RESET VCC1-POWERED REGISTERS SUMMARY

Offset

00h

Chip Sleep Enable Register (CHIP_SLP_EN)

04h

Chip Clock Required Status Registers (CHIP_CLK_REQ_STS)

08h

EC Sleep Enable Register (EC_SLP_EN)

0Ch

EC Clock Required Status Registers (EC_CLK_REQ_STS)

10h

Host Sleep Enable Register (HOST_SLP_EN)

14h

Host Clock Required Status Registers (HOST_CLK_REQ)

18h

System Sleep Control Register (SYS_SLP_CNTRL)

20h

Processor Clock Control Register (PROC_CLK_CNTRL)

24h

EC Sleep Enable 2 Register (EC_SLP_EN2)

28h

EC Clock Required 2 Status Register (EC_CLK_REQ2_STS)

2Ch

Slow Clock Control Register (SLOW_CLK_CNTRL)

30h

Oscillator ID Register (CHIP_OSC_ID)

34h

PCR chip sub-system power reset status (CHIP_PWR_RST_STS)

38h

Chip Reset Enable Register (CHIP_RST_EN)

3Ch

Host Reset Enable Register (HOST_RST_EN)

40h

EC Reset Enable Register (EC_RST_EN)

44h

EC Reset Enable 2 Register (EC_RST_EN2)

48h

Power Reset Control (PWR_RST_CTRL) Register

Note:

All register addresses are naturally aligned on 32-bit boundaries. Offsets for registers that are smaller than

32 bits are reserved and must not be used for any other purpose.

Offset

00h

Bits

Description

Type

Default

Reset

Event

31:2 RESERVED

RES

1 MCHP Reserved (Note 3-10)R/W

VCC1_R

ESET

0 MCHP Reserved (Note 3-10)R/W

VCC1_R

ESET

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