MEC1322 datasheet(77/456 Pages) MICROCHIP

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DS00001719D-page 77

MEC1322

5.4.2

The registers defined for the LPC Interface block are accessible by the various hosts as indicated in Section 5.9, "LPC

Configuration Registers", Section 5.11, "EC-Only Registers"and Section 5.10, "Runtime Registers".

5.5

Power, Clocks and Reset

This section defines the Power, Clock, and Reset parameters of the block.

5.5.1

POWER DOMAINS

5.5.2

CLOCK INPUTS

5.5.3

RESETS

The following table defines the effective reset state that result from the combination of these three reset signals.

LFRAME#

Input

Active low signal indicates start of new cycle and termina-

tion of broken cycle.

LRESET#

Input

Active low signal used as LPC Interface Reset. Same as

PCI Reset on host.

Note:

LRESET# is typically connected to the host

PCI RESET (PCIRST#) signal.

LCLK

Input

PCI clock input (PCI_CLK)

SERIRQ

Input/Output

Serial IRQ pin used with the LCLK signal to transfer inter-

rupts to the host.

CLKRUN#

Open-Drain Output

Clock Control for LCLK

TABLE 5-3:

POWER SOURCES

Name

Description

VCC1

The LPC Interface block and registers are

TABLE 5-4:

CLOCK INPUTS

Name

Description

LCLK

This LPC Interface has a single clock input,

called LCLK.

Note:

The PCI_CLK input to LCLK can run at 19.2MHz to 33MHz. When the PCI_CLK input frequency is from

19.2MHz (including 24MHz) to 33MHz the Handshake bit in the EC Clock Control Register must be set to

a ‘1’ to capture LPC transactions properly. See Section 5.11.4, "EC Clock Control Register," on page 96.

TABLE 5-5:

RESET SIGNALS

Name

Description

VCC1_RESET

Power on Reset to the block. This signal resets all the register and logic

in this block to its default state.

nSIO_RESET

This signal is used to indicate when the main power rail in the system is

reset. The LPC interface is operational when main power is present. This

signal is used to reset selected registers as defined in the Register

Interfaces descriptions.

LRESET#

The LRESET# signal comes from the LPC pin interface. This signal is

defined in the Intel® Low Pin Count (LPC) Interface Specification, v1.1.

TABLE 5-2:

SIGNAL DESCRIPTION TABLE (CONTINUED)

Name

Direction

Description

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