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MEC1322 Datasheet(PDF) 268 Page - Microchip Technology |
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MEC1322 Datasheet(HTML) 268 Page - Microchip Technology |
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268 / 456 page ![]() MEC1322 DS00001719D-page 268 2014 - 2015 Microchip Technology Inc. 18 LOCK_CHANNEL This is used to lock the arbitration of the Channel Arbiter on this channel once this channel is granted. Once this is locked, it will remain on the arbiter until it has completed it transfer (either the Transfer Aborted, Transfer Done or Transfer Terminated conditions). Note: This setting may starve other channels if the locked chan- nel takes an excessive period of time to complete. RW 0h RESET 17 INCREMENT_DEVICE_ADDRESS This will enable an auto-increment to the DMA Channel Device Address. 1: Increment the DMA Channel Device Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0: Do nothing RW 0h RESET 16 INCREMENT_MEMORY_ADDRESS This will enable an auto-increment to the DMA Channel Memory Address. 1=Increment the DMA Channel Memory Address by DMA Channel Control:Transfer Size after every Data Packet transfer 0=Do nothing Note: If this is not set, the DMA will never terminate the transfer on its own. It will have to be terminated through the Hard- ware Flow Control or through a DMA Channel Con- trol:Transfer Abort. RW 0h RESET 15:9 HARDWARE_FLOW_CONTROL_DEVICE This is the device that is connected to this channel as its Hardware Flow Control master. The Flow Control Interface is a bus with each master concatenated onto it. This selects which bus index of the concatenated Flow Con- trol Interface bus is targeted towards this channel. The Flow Control Interface Port list is dma_req, dma_term, and dma_done . RW 0h RESET 8 TRANSFER_DIRECTION This determines the direction of the DMA Transfer. 1=Data Packet Read from Memory Start Address followed by Data Packet Write to Device Address 0=Data Packet Read from Device Address followed by Data Packet Write to Memory Start Address RW 0h RESET 7:6 Reserved R - - 5BUSY This is a status signal. 1=The DMA Channel is busy (FSM is not IDLE) 0=The DMA Channel is not busy (FSM is IDLE) RO 0h RESET Offset 10h Bits Description Type Default Reset Event |
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