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PI6CDBL402B Datasheet(PDF) 4 Page - Pericom Semiconductor Corporation |
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PI6CDBL402B Datasheet(HTML) 4 Page - Pericom Semiconductor Corporation |
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4 / 13 page ![]() 44 All trademarks are property of their respective owners. www.pericom.com 06/30/15 PI6CDBL402B 4 -Output Low Power PCIE GEN 1-2-3 Buffer Data Byte 0: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin 0 Reserved NA 1 PLL/BYPASS# 0 = Fanout 1 = PLL RW 1 = PLL OUT[0:3], OUT[0:3]# NA 2 PLL Bandwidth 0 = High Bandwidth, 1 = Low Bandwidth RW 1 = Low OUT[0:3], OUT[0:3]# NA 3 Reserved NA 4 Reserved NA 5 Reserved NA 6 Reserved NA 7 PD_Mode Refer Power Management Table RW 0 OUT[0:3], OUT[0:3]# NA Data Byte 1: Control Register Bit Descriptions Type Power Up Condition Output(s) Affected Source Pin 0 Reserved NA 1 OUTPUTS enable 1 = Enabled 0 = Disabled RW 1 = Enabled OUT0, OUT0# NA 2 RW 1 = Enabled OUT1, OUT1# NA 3 Reserved NA 4 Reserved NA 5 OUTPUTS enable 1 = Enabled 0 = Disabled RW 1 = Enabled OUT2, OUT2# NA 6 RW 1 = Enabled OUT3, OUT3# NA 7 Reserved NA 15-0083 |
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