99

All trademarks are property of their respective owners.

www.pericom.com

06/30/15

PI6CDBL402B

4 -Output Low Power PCIE GEN 1-2-3 Buffer

Electrical Characteristics–Input/Supply/Common Parameters–Normal Operating

o

C; SVDD = 3.3V+/-10%; VDDO = 3.3V+/-10%, VDDO = 2.5V+/-10%, VDDO = 1.8V+/-

10%, See Test Loads for Loading Conditions)

Symbol

Parameters

Condition

Min.

Type Max. Units

V

Supply voltage for core, analog

3.0

3.3

3.6

V

V

DDO

3.3V Operation

2.97

3.3

3.63

V

2.5V Operation

2.25

2.5

2.75

1.8V Operation

1.62

1.8

1.98

V

IH

Single-ended inputs, except SMBus

0.65

V

DD

V

0.3

V

V

IL

Single-ended inputs, except SMBus

-0.3

0.35

V

DD

V

V

IH

Single-ended outputs, except SMBus. I

V

0.45

V

V

IL

Single-ended outputs, except SMBus. I

0.45

V

I

IN

Single-ended inputs, V

-5

5

uA

I

INP

Single-ended inputs

V

V

tors

-200

200

uA

F

ibyp

Bypass mode

1

400

MHz

F

ipll100

100MHz PLL mode

95

100.00 105

MHz

Lpin

7

nH

C

IN

Logic Inputs, except DIF_IN

1.5

5

pF

C

INDIF_IN

DIF_IN differential clock inputs

1.5

2.7

pF

C

OUT

Output pin capacitance

6

pF

T

STAB

From V

stabilization or de-assertion of PD# to 1st clock

0.6

1

ms

f

MODIN

Input SS Modulation

Allowable Frequency

(Triangular Modulation)

30

31.500 33

kHz

t

LATOE#

DIF start after OE# assertion

DIF stop after OE# deassertion

1

3

clocks

t

DRVPD

DIF output enable after

PD# de-assertion

300

us

t

F

Fall time of single-ended control inputs

5

ns

t

R

Rise time of single-ended control inputs

5

ns

V

ILSMB

SMBus Input Low

0.8

V

V

IHSMB

SMBus Input High

2.1

3.6

V

15-0083