PI6CDBL402B datasheet(1/13 Pages) PERICOM

Part #	PI6CDBL402B

Description	4 -Output Low Power PCIE GEN 1-2-3 Buffer

PDF	13 Pages

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Manufacturer	PERICOM [Pericom Semiconductor Corporation]

Direct Link	http://www.pericom.com

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www.pericom.com

06/30/15

PI6CDBL402B

Block Diagram

Pin Configuration

Description

Pericom Semiconductor's PI6CDBL402B is a PCIe 3.0 compliant

high-speed, low-noise differential clock buffer designed to be

companion to PCIe 3.0 clock generator. It is backward compat-

ible with PCIe 1.0 and 2.0 specification.

The device distributes the differential SRC clock from PCIe 3.0

clock generator to four differential pairs of clock outputs either

with or without PLL. The clock outputs are controlled by input

selection of PWRDWN# and SMBus, SCLK and SDA.

Features

Î

Phase jitter filter for PCIe 3.0/ 2.0/ 1.0 application

Î

Low power consumption with independent output power

supply 1.8V~3.3V

Î

Low skew < 60ps

Î

Low cycle-to-cycle jitter - 45ps (typ.) @100MHz

Î

< 1 ps additive RMS phase jitter

Î

Output Enable for all outputs

Î

Programmable PLL Bandwidth

Î

100 MHz PLL Mode operation

Î

1 - 400 MHz Bypass Mode operation

Î

3.3V Operation

Î

Packaging (Pb-free and Green):

-28-Pin TSSOP (L28)

4 -Output Low Power PCIE GEN 1-2-3 Buffer

OUT0

OUT0#

OUT1

OUT1#

OUT2

OUT2#

OUT3

OUT3#

Output

Control

SMBus

Controller

PLL

PLL_BW#

SRC

SRC#

PLL/BYPASS#

SCLK

SDA

OE_INV

OE_0 & OE_3

PWRDWN#

VDD_A

GNDA

OE_INV

OUT3

OUT3#

OE_3

OUT2

OUT2#

PLL_BW#

VDD

PWRDWN#

28

27

26

25

24

23

22

21

20

19

18

17

16

15

1

2

3

4

5

6

7

8

9

10

11

12

13

14

VDD

SRC

SRC#

GND

VDDO

OUT0

OUT0#

OE_0

OUT1

OUT1#

PLL/BYPASS#

SCLK

SDA

NC

VDDO

PLL/BYPASS#

15-0083

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PI6CDBL402B Datasheet(PDF) 1 Page - Pericom Semiconductor Corporation

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