PI6CDBL402B datasheet(2/13 Pages) PERICOM

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06/30/15

PI6CDBL402B

4 -Output Low Power PCIE GEN 1-2-3 Buffer

Pin Description

Pin #

Pin Name

Type

Description

2, 3

SRC & SRC#

Input

0.7V Differential SRC input from PI6C410 clock synthesizer

8, 21

OE_0 & OE_3

Input

3.3V LVTTL input for enabling outputs, active high.

OE_0 for OUT0 / OUT0#

OE_3 for OUT3 / OUT3#

OE_INV

Input

3.3V LVTTL input for inverting the OE and PWRDWN# pins.

When 0 = same stage

When 1 = OE_0, OE_3, PWRDWN# inverted.

6, 7, 9, 10, 19, 20, 22, 23 OUT[0:3] & OUT[0:3]# Output

0.7V Differential outputs, refer Power Management Table for

detail output status

PLL/BYPASS#

Input

3.3V LVTTL input for selecting fan-out of PLL operation.

SCLK

Input

SMBus compatible SCLOCK input

SDA

I/O

SMBus compatible SDATA

No Connect

PLL_BW#

Input

3.3V LVTTL input for selecting the PLL bandwidth

PWRDWN#

Input

3.3V LVTTL input for Power Down operation, active low

5, 11, 18, 24

DDO

Power

Power supply for outputs, range from 1.8V~3.3V

GND

Ground Ground for Outputs

GNDA

Ground Ground for PLL

DD_A

Power

3.3V Power Supply for PLL

1, 16

Power

3.3V Power Supply for PLL

15-0083

PI6CDBL402B Datasheet(PDF) 2 Page - Pericom Semiconductor Corporation

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