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06/30/15

PI6CDBL402B

4 -Output Low Power PCIE GEN 1-2-3 Buffer

Serial Data Interface (SMBus)

This part is a slave only device that supports blocks read and block write protocol using a single 7-bit address and read/write bit as

shown below.

Read and write block transfers can be stopped after any complete byte transfer by issuing STOP.

Address Assignment

A6

A5

A4

A3

A2

A1

A0

W/R

1

1

0

1

1

1

0

0/1

Data Protocol

1 bit

7 bits

1

1

8 bits

1

8 bits

1

8 bits

1

8 bits

1

1 bit

Start

bit

Slave

Addr

R/W Ack

Register

offset

Ack

Byte

Count

= N

Ack

Data

Byte 0

Ack

…

Data

Byte N

- 1

Ack

Stop bit

Notes:

1. Register offset for indicating the starting register for indexed block write and indexed block read. Byte Count in write mode cannot be 0.

Output[1]/ Output[2] state choose

OE_INV

PWRDWN#

Byte0/Bit7

OE(Pin)

OE(SMBus bit) OUT1/ OUT2 OUT1#/ OUT2#

0

X

X

NA

0

LOW

LOW

0

0

0

NA

1

HIGH

LOW

0

0

1

NA

X

LOW

LOW

0

1

X

NA

1

Clock output

Clock output

1

X

X

NA

0

LOW

LOW

1

1

0

NA

1

HIGH

LOW

1

1

1

NA

X

LOW

LOW

1

0

X

NA

1

Clock output

Clock output

Notes:

1. all registers can’t be written/read during PWRDWN# active

Power Management Table

Output[0]/ Output[3] state choose

OE_INV

PWRDWN#

Byte0/Bit7 OE_0/OE_3(Pin) OE(SMBus bit) OUT0/ OUT3 OUT0#/ OUT3#

0

X

X

0

X

LOW

LOW

0

X

X

X

0

LOW

LOW

0

0

0

1

1

HIGH

LOW

0

0

1

X

X

LOW

LOW

0

1

X

1

1

Clock output

Clock output

1

X

X

1

X

LOW

LOW

1

X

X

X

0

LOW

LOW

1

1

0

0

1

HIGH

LOW

1

1

1

X

X

LOW

LOW

1

0

X

0

1

Clock output

Clock output

15-0083