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06/30/15

PI6CDBL402B

4 -Output Low Power PCIE GEN 1-2-3 Buffer

o

C; VDD = 3.3V+/-10%; VDDO = 3.3V+/-

10%, VDDO = 2.5V+/-10%, VDDO = 1.8V+/-10%, See Test Loads for Loading Conditions)

Symbol Parameters

Condition

Min.

Type

Max.

Units

I

DDOP

Total power consumption, All outputs active

@100MHz, typical value under VDDO = 1.8V

50

60

mA

Total power consumption, All outputs active

@100MHz PLL bypass mode, typical value

under VDDO = 1.8V

24

28

mA

I

DDPD

Total power consumption, Outputs Low

1.3

mA

Note:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Input clock stopped.

Loading Conditions)

Symbol

Parameters

Condition

Min.

Type

Max.

Units

t

DC

Measured differentially, PLL Mode

45

55

%

t

DCD

Measured differentially, Bypass Mode

@100MHz

-1.3

0

1.3

%

t

pdBYP

Bypass Mode, VT = 50%

2500

5000

ps

t

pdPLL

PLL Mode VT = 50%

-260

260

ps

t

skew

PLL Mode VT = 50%

60

ps

t

jcyc-cyc

PLL mode

60

ps

Additive Jitter in Bypass Mode

25

ps

Note:

1. Guaranteed by design and characterization, not 100% tested in production.

2. Measured from differential waveform

3. Duty cycle distortion is the difference in duty cycle between the output and the input clock when the device is operated in bypass mode.

4. All outputs at default slew rate

5. The MIN/TYP/MAX values of each BW setting track each other, i.e., Low BW MAX will never occur with Hi BW MIN.

15-0083