TMP320C2811PBKA datasheet(33/147 Pages) TI

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Functional Overview

June 2004

SPRS257

3.2.8

Boot ROM

The Boot ROM is factory programmed with boot-loading software that can be used to download software from

an external interface. Boot-mode signals are provided that tell the bootloader software which boot mode to

use on power up. The Boot ROM on R281x devices is identical to that on F281x devices, except that the jump

to flash and jump to OTP modes are not available. The Boot Rom also contains standard tables such as

SIN/COS waveforms, for use in math-related algorithms.

3.2.9

Security

R281x devices contain a non−utilizable code security module for compatibility with C281x and F281x devices.

The passwords for the security module are hard-wired in the device as all 0xFFFF. After a device reset, the

L0 and L1 SARAM blocks are in a locked condition until a dummy read of the passwords is performed. The

R281x Boot ROM performs a dummy read of the password locations. If execution after reset begins directly

in external memory on R2812 devices (i.e., MP/MC =1 ), the user should perform 8 dummy reads, one each

from address 0x3F7FF8 through 0x3F7FFF.

3.2.10 Peripheral Interrupt Expansion (PIE) Block

The PIE block serves to multiplex numerous interrupt sources into a smaller set of interrupt inputs. The PIE

block can support up to 96 peripheral interrupts. On R281x, 45 of the possible 96 interrupts are used by

peripherals. The 96 interrupts are grouped into blocks of 8 and each group is fed into 1 of 12 CPU interrupt

lines (INT1 to INT12). Each of the 96 interrupts is, supported by its own vector stored in a dedicated RAM block

that can be overwritten by the user. The vector is, automatically fetched by the CPU on servicing the interrupt.

It takes 8 CPU clock cycles to fetch the vector and save critical CPU registers. Hence the CPU can quickly

respond to interrupt events. Prioritization of interrupts is controlled in hardware and software. Each individual

interrupt can be enabled/disabled within the PIE block.

3.2.11 External Interrupts (XINT1, 2, 13, XNMI)

R281x supports three masked external interrupts (XINT1, 2, 13). XINT13 is combined with one non-masked

external interrupt (XNMI). The combined signal name is XNMI_XINT13. Each of the interrupts can be selected

for negative or positive edge triggering and can also be enabled/disabled (including the XNMI). The masked

interrupts also contain a 16-bit free running up counter, which is reset to zero when a valid interrupt edge is

detected. This counter can be used to accurately time stamp the interrupt.

3.2.12 Oscillator and PLL

R281x can be clocked by an external oscillator or by a crystal attached to the on-chip oscillator circuit. A PLL

is provided supporting up to 10-input clock-scaling ratios. The PLL ratios can be changed on-the-fly in

software, enabling the user to scale back on operating frequency if lower power operation is desired. Refer

to the Electrical Specification section for timing details. The PLL block can be set in bypass mode.

3.2.13 Watchdog

R281x supports a watchdog timer. The user software must regularly reset the watchdog counter within a

certain time frame; otherwise, the watchdog will generate a reset to the processor. The watchdog can be

disabled if necessary.

3.2.14 Peripheral Clocking

The clocks to each individual peripheral can be enabled/disabled so as to reduce power consumption when

a peripheral is not in use. Additionally, the system clock to the serial ports (except eCAN) and the event

managers, CAP and QEP blocks can be scaled relative to the CPU clock. This enables the timing of

peripherals to be decoupled from increasing CPU clock speeds.

TMP320C2811PBKA Datasheet(PDF) 33 Page - Texas Instruments

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