TMP320C2811PBKA datasheet(93/147 Pages) TI

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Electrical Specifications

June 2004

SPRS257

tw(RSL1)

th(XPLLDIS)

th(XMP/MC)

th(boot-mode)

(see Note C)

VDDIO, VDDAn†,

VDDAIO (3.3 V)

(See Note A)

XCLKIN

2.5 V

0.3 V

XRS

XF/XPLLDIS

XMP/MC

Boot-Mode Pins

VDD, VDD1

(1.8 V (or 1.9 V))

XCLKOUT

I/O Pins

User-Code Dependent

Boot-ROM Execution Starts

Peripheral/GPIO Function

Based on Boot Code

GPIO Pins as Input

XPLLDIS Sampling

GPIOF14

XCLKIN/8 (See Note B)

GPIO Pins as Input (State Depends on Internal PU/PD)

tOSCST

(Don’t Care)

User-Code Dependent

Address/Data/

Control

Address/Data Valid. Internal Boot-ROM Code Execution Phase

User-Code Execution Phase

NOTES: A. VDDAn − VDDA1/VDDA2 and AVDDREFBG

B. Upon power up, SYSCLKOUT is XCLKIN/2 if the PLL is enabled. Since both the XTIMCLK and CLKMODE bits in the

XINTCNF2 register come up with a reset state of 1, SYSCLKOUT is further divided by 4 before it appears at XCLKOUT. This

explains why XCLKOUT = XCLKIN/8 during this phase.

C. After reset, the Boot ROM code executes instructions for 1260 SYSCLKOUT cycles (SYSCLKOUT = XCLKIN/2) and then

samples BOOT Mode pins. Based on the status of the Boot Mode pin, the boot code branches to destination memory or boot

code function in ROM. The BOOT Mode pins should be held high/low for at least 2520 XCLKIN cycles from boot ROM

execution time for proper selection of Boot modes.

If Boot ROM code executes after power-on conditions (in debugger environment), the Boot code execution time is based on

the current SYSCLKOUT speed. The SYSCLKOUT will be based on user environment and could be with or without PLL

enabled.

D. The state of the GPIO pins is undefined (i.e., they could be input or output) until the 1.8-V (or 1.9-V) supply reaches at least

1 V and 3.3-V supply reaches 2.5 V.

td(EX)

See Note D

tsu(XPLLDIS)

Figure 6−6. Power-on Reset in Microcomputer Mode (XMP/MC = 0)

TMP320C2811PBKA Datasheet(PDF) 93 Page - Texas Instruments

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