TMP320C2811PBKA datasheet(74/147 Pages) TI

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Peripherals

June 2004

SPRS257

The SPI module features include:

•

Four external pins:

−

SPISOMI: SPI slave-output/master-input pin

−

SPISIMO: SPI slave-input/master-output pin

−

SPISTE: SPI slave transmit-enable pin

−

SPICLK: SPI serial-clock pin

NOTE: All four pins can be used as GPIO, if the SPI module is not used.

•

Two operational modes: master and slave

•

Baud rate: 125 different programmable rates

−

Baud rate =

LSPCLK

(SPIBRR ) 1)

, when BRR ≠ 0

= LSPCLK

when BRR = 0, 1, 2, 3

Serial port performance is limited by I/O buffer switching speed. Internal prescalers must be adjusted

such that the peripheral speed is less than the I/O buffer speed limit—20 MHz maximum.

•

Data word length: one to sixteen data bits

•

Four clocking schemes (controlled by clock polarity and clock phase bits) include:

−

Falling edge without phase delay: SPICLK active-high. SPI transmits data on the falling edge of the

SPICLK signal and receives data on the rising edge of the SPICLK signal.

−

Falling edge with phase delay: SPICLK active-high. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the falling edge of the SPICLK signal.

−

Rising edge without phase delay: SPICLK inactive-low. SPI transmits data on the rising edge of the

SPICLK signal and receives data on the falling edge of the SPICLK signal.

−

Rising edge with phase delay: SPICLK inactive-low. SPI transmits data one half-cycle ahead of the

falling edge of the SPICLK signal and receives data on the rising edge of the SPICLK signal.

•

Simultaneous receive and transmit operation (transmit function can be disabled in software)

•

Transmitter and receiver operations are accomplished through either interrupt-driven or polled

algorithms.

•

Nine SPI module control registers: Located in control register frame beginning at address 7040h.

All registers in this module are 16-bit registers that are connected to Peripheral Frame 2. When a register

is accessed, the register data is in the lower byte (7−0), and the upper byte (15−8) is read as zeros. Writing

to the upper byte has no effect.

Enhanced feature:

•

16-level transmit/receive FIFO

•

Delayed transmit control

TMP320C2811PBKA Datasheet(PDF) 74 Page - Texas Instruments

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