TMP320C2811PBKA datasheet(92/147 Pages) TI

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Electrical Specifications

June 2004

SPRS257

6.13.2 Output Clock Characteristics

Table 6−7. XCLKOUT Switching Characteristics (PLL Bypassed or Enabled)†‡

No.

PARAMETER

MIN

TYP

MAX

UNIT

tc(XCO)

Cycle time, XCLKOUT

6.67§

tf(XCO)

Fall time, XCLKOUT

tr(XCO)

Rise time, XCLKOUT

tw(XCOL)

Pulse duration, XCLKOUT low

H−2

H+2

tw(XCOH)

Pulse duration, XCLKOUT high

H−2

H+2

PLL lock time

131072tc(CI)

† A load of 40 pF is assumed for these parameters.

‡ H = 0.5tc(XCO)

§ The PLL must be used for maximum frequency operation.

XCLKOUT

(see Note B)

XCLKIN

C10

(see Note A)

NOTES: A. The relationship of XCLKIN to XCLKOUT depends on the divide factor chosen. The waveform relationship shown in Figure 6−5 is

intended to illustrate the timing parameters only and may differ based on configuration.

B. XCLKOUT configured to reflect SYSCLKOUT.

Figure 6−5. Clock Timing

6.14 Reset Timing

Table 6−8. Reset (XRS) Timing Requirements†

MIN

NOM

MAX

UNIT

tw(RSL1)

Pulse duration, stable XCLKIN to XRS high

8tc(CI)

cycles

Pulse duration XRS low

Warm reset

8tc(CI)

cycles

tw(RSL2)

Pulse duration, XRS low

WD-initiated reset

512tc(CI)

cycles

tw(WDRS)

Pulse duration, reset pulse generated by watchdog

512tc(CI)

cycles

td(EX)

Delay time, address/data valid after XRS high

32tc(CI)

cycles

tOSCST‡

Oscillator start-up time

tsu(XPLLDIS)

Setup time for XPLLDIS pin

16tc(CI)

cycles

th(XPLLDIS)

Hold time for XPLLDIS pin

16tc(CI)

cycles

th(XMP/MC)

Hold time for XMP/MC pin

16tc(CI)

cycles

th(boot-mode)

Hold time for boot-mode pins

2520tc(CI)§

cycles

† If external oscillator/clock source are used, reset time has to be low at least for 1 ms after VDD reaches 1.5 V.

‡ Dependent on crystal/resonator and board design.

TMP320C2811PBKA Datasheet(PDF) 92 Page - Texas Instruments

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